Features
- PCIe Gen6 additive phase jitter: 4fs RMS
- PCIe Gen7 additive phase jitter: 2.8fs RMS
- DB2000Q/DB1206 additive phase jitter: 12fs RMS
- 12kHz–20MHz additive phase jitter: 36fs RMS at 156.25MHz
- Power-down tolerant (PDT) inputs
- Flexible startup sequencing (FSS)
- SMBus-enabled automatic clock parking (ACP)
- CLKIN accepts HCSL or LVDS signal levels
- 12 LP-HCSL outputs with 85Ω impedance
9QXL1200 Block Diagram
Description
The 9QXL1200 is an ultra-high performance PCIe Gen7 fanout buffer that is backward compatible with earlier PCIe generations. It features a loss-of-signal (LOS) output for system monitoring and resiliency. The device also incorporates power-down tolerant (PDT) and flexible startup sequencing (FSS) capabilities, simplifying system design.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 12 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 400 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 441 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | LP-HCSL |
| Package Area (mm²) | 25 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 1 - 400 |
| Additive Phase Jitter Typ RMS (fs) | 2.8 |
| Function | Fanout Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Product Category | Clock Buffers & Drivers, PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| LGA | 5.0 x 5.0 x 0.66 | 64 | 0.5 |
Product Comparison
| 9QXL1200 | 9QXL2001C | |
| Core Voltage (V) | 3.3 | 3.3 |
| Output Impedance | 85 | 85 |
| App Jitter Compliance | DB1206, DB2000Q, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7, QPI, UPI | 25G EDR, DB2000Q, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, QPI, UPI |
| VOUT Slew-rate Control | Yes | No |
| Additive Jitter | 4fs | 4fs |
Applications
- Cloud and high-performance computing
- NVMe storage
- Networking
- AI accelerators
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9QXL1200ALWGK | Active | Available | Out of Stock | LGA | 1ku | $2.15 | 64# | Tray | 3 | 0 | 490# | Yes | e3 Sn | -40 to 105°C | TAIWAN | TAIWAN |
| 9QXL1200ALWGK/W | Active | N/A | Out of Stock | LGA | 1ku | $2.15 | 64# | Reel | 3 | 4000# | 0 | Yes | e3 Sn | -40 to 105°C | TAIWAN | TAIWAN |
| 9QXL1200ALWGK8 | Active | N/A | Out of Stock | LGA | 1ku | $2.15 | 64# | Reel | 3 | 4000# | 0 | Yes | e3 Sn | -40 to 105°C | TAIWAN | TAIWAN |
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- Application NotePDF 2.66 MB R31AN0080EU0102 Rev.1.02 Jun 02, 2026AI-generated Summary: Layout recommendations focus on PCIe Buffer/Mux devices across several families, emphasizing optimal PCB layer stack-up, trace sizing, and signal routing. Key points include using microstrip impedance calculations and tools like Polar Instruments for trace design, following common layout rules such as avoiding right-angle bends, and ensuring proper power supply, clocking, EMI-EMC, and thermal layouts. The document provides detailed guidance on signal integrity, current return paths, crosstalk reduction, and EPAD thermal management to enhance PCIe timing device performance.
- Datasheet9QXL1200 DatasheetRECOMMENDED
- Datasheet - Short-Form9QXL1200 Short-Form DatasheetRECOMMENDEDPDF 118 KB R31DO0009EU0100 Rev.1.00 Sep 25, 2025The 9QXL1200 is a high-performance fanout buffer supporting PCIe Gen1–Gen7, ideal for cloud computing, NVMe storage, networking, and AI accelerators. It features ultra-low jitter, flexible startup sequencing, and SMBus-controlled security. This short-form datasheet highlights its key capabilities and integration benefits.
- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 160 KB 7WDXRDKU4E7E-5-57287 May 06, 2014
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Datasheet - Short-Form9QXL1200 Short-Form DatasheetRECOMMENDEDPDF 118 KB R31DO0009EU0100 Rev.1.00 Sep 25, 2025The 9QXL1200 is a high-performance fanout buffer supporting PCIe Gen1–Gen7, ideal for cloud computing, NVMe storage, networking, and AI accelerators. It features ultra-low jitter, flexible startup sequencing, and SMBus-controlled security. This short-form datasheet highlights its key capabilities and integration benefits.
- Datasheet9QXL1200 DatasheetRECOMMENDED
Recommended Documents (2)
- Datasheet9QXL1200 DatasheetRECOMMENDED
- Datasheet - Short-Form9QXL1200 Short-Form DatasheetRECOMMENDEDPDF 118 KB R31DO0009EU0100 Rev.1.00 Sep 25, 2025The 9QXL1200 is a high-performance fanout buffer supporting PCIe Gen1–Gen7, ideal for cloud computing, NVMe storage, networking, and AI accelerators. It features ultra-low jitter, flexible startup sequencing, and SMBus-controlled security. This short-form datasheet highlights its key capabilities and integration benefits.
Datasheets (2)
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- Application NotePDF 2.66 MB R31AN0080EU0102 Rev.1.02 Jun 02, 2026AI-generated Summary: Layout recommendations focus on PCIe Buffer/Mux devices across several families, emphasizing optimal PCB layer stack-up, trace sizing, and signal routing. Key points include using microstrip impedance calculations and tools like Polar Instruments for trace design, following common layout rules such as avoiding right-angle bends, and ensuring proper power supply, clocking, EMI-EMC, and thermal layouts. The document provides detailed guidance on signal integrity, current return paths, crosstalk reduction, and EPAD thermal management to enhance PCIe timing device performance.
- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- White PaperPDF 1.35 MB 7WDXRDKU4E7E-6-61930 Aug 05, 2020As PCIe data rates increase and jitter budgets tighten, accurately measuring reference clock jitter becomes more challenging. This paper examines how intrinsic jitter in test setups impacts measurement accuracy and compares results from Phase Noise Analyzers and digital sampling oscilloscopes. It also explores methods to isolate and correct for intrinsic jitter using noiseless PCIe Gen5 clock sources and real-world components such as fan-out buffers and clock generators.View More (10)
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The RC family consists of PCIe Gen7 clock buffer and multiplexer solutions, providing the industry's smallest and most compact footprint.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas).
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