Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.
| Pkg. Type: | SSOP |
| Pkg. Code: | PYG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 10.2 x 5.3 x 1.73 |
| Pitch (mm): | 0.65 |
| Pb (Lead) Free | Yes |
| Moisture Sensitivity Level (MSL) | 1 |
| ECCN (US) | |
| HTS (US) |
| Pkg. Type | SSOP |
| Lead Count (#) | 28 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Accepts Spread Spec Input | Yes |
| Advanced Features | Accepts Spread Spec Input, Reference Output |
| App Jitter Compliance | DDR2 |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 1.8 |
| Delay Mode | Variable |
| Die Form | No |
| Diff. Input Signaling | SSTL-2 |
| Diff. Output Signaling | SSTL-2 |
| Function | Buffer |
| Input Freq (MHz) | 125 - 400 |
| Inputs (#) | 0 |
| Length (mm) | 10.2 |
| MOQ | 141 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 125 - 400 |
| Output Skew (ps) | 40 |
| Output Type | SSTL-2 |
| Output Voltage (V) | 1.8 |
| Outputs (#) | 6 |
| Package Area (mm²) | 54.1 |
| Pb Free Category | e3 Sn |
| Period Jitter Max P-P (ps) | 30 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 10.2 x 5.3 x 1.73 |
| Qty. per Carrier (#) | 47 |
| Qty. per Reel (#) | 0 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Supply Voltage (V) | 1.8 - 1.8 |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1.73 |
| Width (mm) | 5.3 |
DDR II fanout buffer for VIA Chipset
