9FGV1005

Features

PCIe Gen 1–5 compliant
PCIe Gen 5 Common Clock jitter < 80fs RMS
284fs RMS typical phase jitter at 156.25MHz (12kHz to 20MHz)
2 programmable output pairs plus 1 LVCMOS REF outputs
1 integer output frequency per configuration
1MHz to 325MHz output frequency (LVDS or LP-HCSL)
1MHz to 200MHz output frequency (LVCMOS)
1.8V to 3.3V core V_DD
Individual 1.8V to 3.3V V_DDO for each programmable output pair
Supports HCSL, LVDS, and LVCMOS I/O standards
Supports AC-coupled LVPECL and CML logic – See AN-891
3mm × 3mm 16-LGA packages with 50MHz integrated crystal option
Supported by Timing Commander™ software

Find Other Products in Application-Specific Clocks

9FGV1005Q5 - Pinout (integrated crystal)

9FGV1005 - Block Diagram

Description

The 9FGV1005 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1005 provides two copies of a single non-spread spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

This device is factory-configurable.
Try the Custom Part Configuration Utility.

Parameters

Attributes	Value
Diff. Outputs	2
Diff. Output Signaling	LP-HCSL
Output Freq Range (MHz)	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25, 161.1328125 - 161.1328125, 312.5 - 312.5, 322.265625 - 322.265625, 156.25 - 156.25
Accepts Spread Spec Input	No
Power Consumption Typ (mW)	100
Supply Voltage (V)	1.8 - 1.8, 3.3 - 3.3
Output Type	LP-HCSL
Xtal Freq (MHz)	25 - 25, 39.0625 - 39.0625, 50 - 50
Package Area (mm²)	25
Battery Backup	No
Battery Seal	No
CPU Supervisory Function POR	No
Crystal Frequency Trimming	No
Frequency Out Pin	No
Inputs (#)	1
Input Freq (MHz)	25 - 25, 39.0625 - 39.0625, 50 - 50
Function	Generator
Input Type	Crystal, LVCMOS
Output Banks (#)	1
Core Voltage (V)	1.8, 3.3
Output Voltage (V)	1.8, 3.3
Product Category	PhiClock, PCI Express Clocks, Programmable Clocks

Package Options

Pkg. Type	Pkg. Dimensions (mm)	Lead Count (#)	Pitch (mm)
LGA	3.0 x 3.0 x 1.1	16	0.5

This device is factory-configurable.
Try the Custom Part Configuration Utility.

Part Number	Status	Samples	Longevity	Stock	Package	Budgetary Price (USD)	Lead Count (#)	Carrier Type	Moisture Sensitivity Level (MSL)	Phase Jitter Typ RMS (ps)	Input Freq (MHz)	Xtal Freq (MHz)	Core Voltage (V)	Diff. Output Signaling	Output Freq Range (MHz)	Output Type	Output Voltage (V)	Supply Voltage (V)	Advanced Features	App Jitter Compliance	Input Type	Outputs (#)	Output Impedance	Power Consumption Typ (mW)	Prog. Clock	Qty. per Reel (#)	Spread Spectrum	Qty. per Carrier (#)	Xtal Inputs (#)	Pb (Lead) Free	Pb Free Category	Temp. Range (°C)	Country of Assembly	Country of Wafer Fabrication
9FGV1005C001LTGI	Active	Available	2040 Apr	Out of Stock	LGA		16#	Tray	3	0.267ps	25 - 25	25 - 25	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C001LTGI8	Active	N/A	2040 Apr	Out of Stock	LGA		16#	Reel	3	0.267ps	25 - 25	25 - 25	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C002LTGI	Active	Available	2040 Apr	Out of Stock	LGA		16#	Tray	3	0.304ps	25 - 25	25 - 25	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C002LTGI8	Active	N/A	2040 Apr	Out of Stock	LGA		16#	Reel	3	0.304ps	25 - 25	25 - 25	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C011LTGI	Active	Available	2040 Apr	Out of Stock	LGA		16#	Tray	3	0.234ps	39.0625 - 39.0625	39.0625 - 39.0625	3.3V	LP-HCSL	161.1328125 - 161.1328125, 312.5 - 312.5, 322.265625 - 322.265625, 156.25 - 156.25	LP-HCSL	3.3V	3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C011LTGI8	Active	N/A	2040 Apr	Out of Stock	LGA		16#	Reel	3	0.234ps	39.0625 - 39.0625	39.0625 - 39.0625	3.3V	LP-HCSL	161.1328125 - 161.1328125, 312.5 - 312.5, 322.265625 - 322.265625, 156.25 - 156.25	LP-HCSL	3.3V	3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C012LTGI	Active	Available	2040 Apr	Out of Stock	LGA		16#	Tray	3	0.262ps	39.0625 - 39.0625	39.0625 - 39.0625	1.8V	LP-HCSL	161.1328125 - 161.1328125, 312.5 - 312.5, 322.265625 - 322.265625, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005C012LTGI8	Active	N/A	2040 Apr	Out of Stock	LGA		16#	Reel	3	0.262ps	39.0625 - 39.0625	39.0625 - 39.0625	1.8V	LP-HCSL	161.1328125 - 161.1328125, 312.5 - 312.5, 322.265625 - 322.265625, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005CQ505LTGI	Active	Available	2040 Apr	In Stock	LGA	1ku \| $2.74	16#	Tray	3	0.223ps	50 - 50	50 - 50	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	0	No	490#	1#	Yes	e4 Au	-40 to 85°C	TAIWAN	SINGAPORE
9FGV1005CQ505LTGI8	Active	N/A	2040 Apr	Out of Stock	LGA	1ku \| $2.74	16#	Reel	3	0.223ps	50 - 50	50 - 50	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C	TAIWAN	SINGAPORE
9FGV1005CQ506LTGI	Active	Available	2040 Apr	In Stock	LGA	1ku \| $2.74	16#	Tray	3	0.273ps	50 - 50	50 - 50	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	0	No	490#	1#	Yes	e4 Au	-40 to 85°C	TAIWAN	SINGAPORE
9FGV1005CQ506LTGI8	Active	N/A	2040 Apr	Out of Stock	LGA	1ku \| $2.74	16#	Reel	3	0.273ps	50 - 50	50 - 50	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5	Crystal, LVCMOS	2#	100	100mW	Yes	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C	TAIWAN	SINGAPORE
9FGV1005A000LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	8 - 50	8 - 50	1.8V, 2.5V, 3.3V	LP-HCSL, LVDS	10 - 325	LP-HCSL, LVCMOS, LVDS	1.8V, 2.5V, 3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Reference Output, Spread Spectrum, Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	3#	85, 100	100mW	No	0	Yes	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A000LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	8 - 50	8 - 50	1.8V, 2.5V, 3.3V	LP-HCSL, LVDS	10 - 325	LP-HCSL, LVCMOS, LVDS	1.8V, 2.5V, 3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Reference Output, Spread Spectrum, Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	3#	85, 100	100mW	No	3000#	Yes	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A001LTGI	NRND	Available		In Stock	LGA		16#	Tray	3	0.246ps	25 - 25	25 - 25	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	125mW	No	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A001LTGI8	NRND	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	25 - 25	25 - 25	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	125mW	No	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A002LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	25 - 25	25 - 25	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	100mW	No	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A002LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	25 - 25	25 - 25	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	100mW	No	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A003LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.291ps	25 - 25	25 - 25	3.3V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	125mW	No	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A003LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	25 - 25	25 - 25	3.3V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	125mW	No	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A004LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	25 - 25	25 - 25	1.8V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	100mW	No	0	No	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005A004LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	25 - 25	25 - 25	1.8V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	2#	100	100mW	No	3000#	No	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005Q500LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	8 - 50	50 - 50	1.8V, 2.5V, 3.3V	LP-HCSL, LVDS	10 - 325	LP-HCSL, LVCMOS, LVDS	1.8V, 2.5V, 3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Reference Output, Spread Spectrum, Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	3#	85, 100	100mW	No	0	Yes	490#	1#	Yes	e4 Au	-40 to 85°C
9FGV1005Q500LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	8 - 50	50 - 50	1.8V, 2.5V, 3.3V	LP-HCSL, LVDS	10 - 325	LP-HCSL, LVCMOS, LVDS	1.8V, 2.5V, 3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Reference Output, Spread Spectrum, Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal, LVCMOS	3#	85, 100	100mW	No	3000#	Yes	0	1#	Yes	e4 Au	-40 to 85°C
9FGV1005Q505LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	50 - 50	50 - 50	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	125mW	No	0	No	490#	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q505LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.267ps	50 - 50	50 - 50	3.3V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	125mW	No	3000#	No	0	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q506LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	50 - 50	50 - 50	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	100mW	No	0	No	490#	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q506LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.304ps	50 - 50	50 - 50	1.8V	LP-HCSL	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LP-HCSL	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	100mW	No	3000#	No	0	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q507LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.291ps	50 - 50	50 - 50	3.3V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	125mW	No	0	No	490#	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q507LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	50 - 50	50 - 50	3.3V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	3.3V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	125mW	No	3000#	No	0	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q508LTGI	Obsolete	N/A		Out of Stock	LGA		16#	Tray	3	0.246ps	50 - 50	50 - 50	1.8V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	100mW	No	0	No	490#	0	Yes	e4 Au	-40 to 85°C
9FGV1005Q508LTGI8	Obsolete	N/A		Out of Stock	LGA		16#	Reel	3	0.246ps	50 - 50	50 - 50	1.8V	LVDS	50 - 50, 100 - 100, 125 - 125, 156.25 - 156.25	LVDS	1.8V	1.8 - 1.8, 2.5 - 2.5, 3.3 - 3.3	Programmable Clock	PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4	Crystal (integrated)	2#	100	100mW	No	3000#	No	0	0	Yes	e4 Au	-40 to 85°C

Filters

Datasheet
9FGV1001C-9FGV1005C Datasheet
RECOMMENDED
PDF 711 KB Nov 10, 2025
Application Note
PLL Loop Filter Design and Fine Tuning
PDF 1.53 MB R31AN0034EU0102 Rev.1.02 Oct 21, 2025
AI-generated Summary: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
Application Note
AN-805 Recommended Ferrite Beads
PDF 91 KB R31AN0042EU0102 Rev.1.02 Aug 11, 2025
Model - IBIS
9FGV100x IBIS Model
ZIP 106 KB Apr 21, 2025
Application Note
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with Universal Low-Power HCSL Outputs
PDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
Application Note
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output
PDF 256 KB Jul 05, 2021
AI-generated Summary: The document explains methods to generate a 1.2V LVCMOS signal from a 1.8V LVCMOS output by attenuating the amplitude without lowering the driver voltage. It details typical LVCMOS driver and receiver configurations, impedance matching using source termination, and the use of a parallel resistor at the receiver input to reduce signal amplitude. Simulation and measurement results demonstrate that adding a parallel resistor effectively lowers the voltage to 1.2V while maintaining signal integrity and minimal impact on jitter and frequency. This approach supports flexible amplitude adjustment for various low-voltage LVCMOS requirements in clock signal applications.
Product Change Notice
PCN# : PCN200009 (R1) PhiClock Family Revision Update
PDF 129 KB Nov 06, 2020
Datasheet Addendum
9FGV1005CQ506 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005CQ505 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005C012 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005C011 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005C002 Datasheet Addendum
PDF 144 KB Sep 15, 2020
Datasheet Addendum
9FGV1005C001 Datasheet Addendum
PDF 144 KB Sep 15, 2020
Product Change Notice
PCN# : PCN200009 PhiClock Family Revision Update
PDF 143 KB Aug 27, 2020
Application Note
Driving Differential, Single-Ended, and/or Frequency Generator Crystal Inputs
PDF 134 KB Jun 18, 2020
AI-generated Summary: Various methods to drive crystal input pins or differential receivers are detailed, including direct LVCMOS clock driving with impedance matching via series resistors to prevent signal distortion. The document covers configurations for single-ended HCSL inputs, LVPECL, LVDS, and coaxial inputs, emphasizing proper voltage levels, coupling methods, and termination resistors. It also explains layout considerations for crystal or clock oscillator inputs, load capacitor variations, and level shifting techniques for different voltage domains. Practical component values and connection guidelines ensure signal integrity and compatibility across multiple interface types.

Datasheets (7)

Datasheet
9FGV1001C-9FGV1005C Datasheet
RECOMMENDED
PDF 711 KB Nov 10, 2025
Datasheet Addendum
9FGV1005CQ506 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005CQ505 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005C012 Datasheet Addendum
PDF 144 KB Sep 16, 2020
Datasheet Addendum
9FGV1005C011 Datasheet Addendum
PDF 144 KB Sep 16, 2020

View More (7)

Manuals & Guides (3)

Manual - Software
9FGV1005 Register Descriptions and Programming Guide
PDF 293 KB 7WDXRDKU4E7E-5-62423 Mar 07, 2018
Manual - Software
9FGV1005 PhiClock PCIe Timing Commander Software User Guide
PDF 1.5 MB 7WDXRDKU4E7E-5-62522 Feb 23, 2018
Manual - Software
9FGV100x Register Descriptions and Programming Guide
PDF 401 KB 7WDXRDKU4E7E-5-62508 Nov 27, 2017

Application Notes & White Papers (19)

Application Note
PLL Loop Filter Design and Fine Tuning
PDF 1.53 MB R31AN0034EU0102 Rev.1.02 Oct 21, 2025
AI-generated Summary: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
Application Note
AN-805 Recommended Ferrite Beads
PDF 91 KB R31AN0042EU0102 Rev.1.02 Aug 11, 2025
Application Note
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with Universal Low-Power HCSL Outputs
PDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
Application Note
AN-827 Application Relevance of Clock Jitter
PDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
Application Note
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output
PDF 256 KB Jul 05, 2021
AI-generated Summary: The document explains methods to generate a 1.2V LVCMOS signal from a 1.8V LVCMOS output by attenuating the amplitude without lowering the driver voltage. It details typical LVCMOS driver and receiver configurations, impedance matching using source termination, and the use of a parallel resistor at the receiver input to reduce signal amplitude. Simulation and measurement results demonstrate that adding a parallel resistor effectively lowers the voltage to 1.2V while maintaining signal integrity and minimal impact on jitter and frequency. This approach supports flexible amplitude adjustment for various low-voltage LVCMOS requirements in clock signal applications.

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Product Notices (PCN, EOL, etc) (2)

Product Change Notice
PCN# : PCN200009 (R1) PhiClock Family Revision Update
PDF 129 KB Nov 06, 2020
Product Change Notice
PCN# : PCN200009 PhiClock Family Revision Update
PDF 143 KB Aug 27, 2020

Marketing Collateral (1)

Overview
PCI Express Timing Solutions Overview
PDF 2.4 MB 7WDXRDKU4E7E-6-62036 Nov 15, 2024

Other (1)

Document
I2C GUI Tool User Guide
PDF 507 KB May 05, 2020

Renesas Boards & Kits

9FGV1005 - Evaluation Board (perspective)

EVK9FGV1005

Evaluation Kit for 9FGV1005 Programmable PhiClock™ Generator

This is the evaluation board for the 9FGV1005 programmable PhiClock^TM generator. It provides a convenient way of configuring and programming the blank parts for the 9FGV1005 device. With the onboard USB interface, the Renesas Timing Commander^TM Graphical User Interface (GUI) can communicate with... Read More

Evaluation Kit for 9FGV1005 Programmable PhiClock™ Generator with Internal 50MHz Crystal

This is the evaluation board for the 9FGV1005Q5 programmable PhiClock^TM generator with internal 50MHz crystal. It provides a convenient way of configuring and programming the blank parts for the 9FGV1005Q5 device. With the onboard USB interface, the Renesas Timing Commander^TM graphical user... Read More

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Software & Tools (2)

Software & Tools - Other
9FGV100x Integer v1.4.2 Timing Commander Personality File
ZIP 3.89 MB Aug 12, 2024
Software & Tools - Software
I2C GUI Tool Software
ZIP 9.27 MB Nov 07, 2022

Simulation Models (1)

Model - IBIS
9FGV100x IBIS Model
ZIP 106 KB Apr 21, 2025

Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

The IDT PhiClock™ 9FGV100x PCIe Gen 4 clock generators combine space savings, high performance and low power in a single, easy-to-use solution. All PhiClock PCIe reference clock devices integrate crystal load capacitors and offer an optional integrated crystal to simplify designs and save board space. When configured with HCSL outputs for PCIe applications, PhiClock products integrate the output termination resistors, further reducing board space. Extremely small 3 x 3 mm and 4 x 4 mm packages complement the integration for maximum space savings. The programmable PhiClock clock generators combine outstanding PCIe Gen4 performance and outstanding Ethernet performance with phase jitter as low as 225fs rms at 156.25MHz (12k-20M). Extremely low power consumption (as low as 100 mW at 1.8V) allows placement closer to high-power components, which also reduces board space requirements.

A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.

Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.

In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.

This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.

An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.

Presented by Ron Wade, System Architect at IDT.

A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.

Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.

News & Blog Posts

Blog Post

Jun 15, 2019

Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility

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Evaluation Kit for 9FGV1005 Programmable PhiClock™ Generator

Evaluation Kit for 9FGV1005 Programmable PhiClock™ Generator with Internal 50MHz Crystal

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