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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

Features

  • Power up default is all outputs in 1:1 mode
  • DIF_(14:0) can be "gear-shifted" from the input CPU Host Clock
  • DIF_(18:15) can be "gear-shifted" from the input CPU Host Clock
  • Spread spectrum compatible
  • Supports output clock frequencies up to 400 MHz
  • 8 Selectable SMBus addresses
  • SMBus address determines PLL or Bypass mode
  • Dedidated Power Down Pin

Description

The IDT9FG1904B-1 follows the Intel DB1900GS Differential Buffer Specification, except for the output groupings. This buffer provides 19 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(14:0) and DIF_(18:15) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the IDT932S421, drives the IDT9FG1904B-1. The IDT9FG1904B-1 can provide outputs up to 400MHz.

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