Features
- Pin-compatible with the 722x5 SuperSync FIFOs
- 10ns read/write cycle time (8ns access time)
- Fixed, low first word data latency time
- Auto power down minimizes standby power consumption
- Retransmit operation with fixed, low first word data latency time
- Empty, Full and Half-Full flags signal FIFO status
- Programmable Almost-Empty and Almost-Full flags
- Easily expandable in depth and width
- Independent Read and Write clocks (permit reading and writing simultaneously)
- Available in 64-pin TQFP and STQFP packages
- Industrial temperature range (–40C to +85C) is available
72265 - Block Diagram
Description
The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data
Parameters
| Attributes | Value |
|---|---|
| Core Voltage (V) | 5 |
| Bus Width (bits) | 18 |
| Density (Kb) | 288 |
| Pkg. Code | PNG64 |
| Interface | Synchronous |
| I/O Type | 5.0 V TTL |
| I/O Frequency (MHz) | 66 - 66 |
| Organization | 16K x 18 |
| Temp. Range (°C) | -40 to 85°C |
| Architecture | Uni-directional |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 14.0 x 14.0 x 1.4 | 64 | 0.8 |
Support Communities
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[sdk5]problem about ext_sleep
Background 1>project name: projects\target_apps\ble_examples\ble_app_profile 2>#undef CFG_DEVELOPMENT_DEBUG in da1458x_config_basic.h 3>for simplify the problem,comment the line ://#include "custs1.h" in user_profiles_config.h; 4>change value of app_default_sleep_mode ...
Dec 7, 2015
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