Features
- True Dual-Ported memory cells which allow simultaneous access of the same memory location
- Separate upper-byte and lower-byte control for multiplexed bus compatibility
- 7026 easily expands data bus width to 32 bits or more
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- TTL-compatible, single 5V (±10%) power supply
- Available in 84-pin PGA and PLCC packages
- Industrial temperature range (-40C to +85C) is available
Description
Parameters
| Attributes | Value |
|---|---|
| Core Voltage (V) | 5 |
| Bus Width (bits) | 16 |
| Density (Kb) | 256 |
| Pkg. Code | GU84 |
| Interface | Async |
| I/O Type | 5.0 V TTL |
| Access Time (ns) | 25, 35 |
| Temp. Range (°C) | 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 16K x 16 |
| Function | Busy, Interrupt, Master, Semaphore, Slave |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| PGA | 27.94 x 27.94 x 3.68 | 84 | 2.54 |
Support Communities
-
Confirm Memory Detail of 70261L15PFG
Hi,As I will be taping out a chip recently, I want to confirm some details with your team regarding the SRAM Verilog behavioral model file you provided. verilog_model.zipThe product I purchased is 70261L15PFG (https://www.mouser.tw/ProductDetail/), and you previously informed me ...
Dec 9, 2024 -
Verilog model for the 70261 (16Kx16)
Dear Renesas Team, Could you provide me with the Verilog behavior model for 70261 SRAM?Thanks! Best Regards,Jason Shih [locked by: Michael Quirk at 15:19 (GMT 0) on 14 Aug 2024]
Jul 30, 2024 -
RX64M Bootloader app
Stikll fighting with the bootloader app but making progress. Current problem is an error message that appears in the console when I download the mot file into flash. Finished downloadStarting downloadFFW Call Error for CFFWInterface::FFWE20Cmd_DWNP_CLOSE:There's no data for option setting memory.Security ID code for ...
Aug 30, 2016
Support Communities
