Overview
Description
The 650-40 is a clock chip designed for use in Ethernet Switch applications. Using IDT’s patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces various output clock frequencies as listed in Output Select Table.
Features
- Packaged in 16-pin TSSOP
- Pb (lead) free package
- Operating voltage of 3.3 V
- Low power consumption
- Input frequency of 25 MHz
- Low long-term jitter
- 2.5 V to 3.3 V clock outputs
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 244 KB | |
| Product Change Notice | PDF 663 KB | |
| End Of Life Notice | PDF 72 KB | |
| End Of Life Notice | PDF 72 KB | |
| Product Change Notice | PDF 361 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
Support Communities
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riic SCLK rate is screwy
Ive got a project S5D9 running in SSP 1.7.5 as an upgrade from SSP1.5 I have a lot of stuff out on the I2C buses and the relevant threads are set up as: One thread that talks to iic1 and one peripheral on it. It runs this ...
May 30, 2020