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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.

Features

  • Guaranteed Low Skew < 60ps (max)
  • Very low duty cycle distortion
  • High speed propagation delay < 2.5ns. (max)
  • Up to 250MHz operation
  • Very low CMOS power levels
  • 1.5V VDDQ for HSTL interface
  • Hot insertable and over-voltage tolerant inputs
  • 3-level inputs for selectable interface
  • Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface
  • Selectable differential or single-ended inputs and five single-ended outputs
  • 2.5V VDD
  • Available in TSSOP package

Description

The 5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The 5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.

Part NumberStatusSamplesStockPackageLead Count (#)Carrier TypeMoisture Sensitivity Level (MSL)Input TypeOutput Skew (ps)Output Voltage (V)Qty. per Reel (#)Qty. per Carrier (#)Pb (Lead) FreePb Free CategoryTemp. Range (°C)
5T905PGGIObsoleteN/AIn StockTSSOP28#Tube1LVCMOS60ps2.5V050#Yese3 Sn-40 to 85°C
5T905PGGI8ObsoleteN/AIn StockTSSOP28#Reel1HSTL, LVTTL, LVCMOS, LVPECL25ps2.5V, 1.8V, 1.5V2000#0Yese3 Sn-40 to 85°C
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