Features
- Packaged in 20-pin TSSOP
- RoHS 5 (green) or RoHS 6 (green and lead free) complaint package
- Supports PCI-Express applications
- Four differential spread spectrum clock outputs
- Spread spectrum for EMI reduction
- Uses external 25 MHz clock or crystal input
- Power down pin turns off chip
- OE control tri-states outputs
- Spread and frequency selection via external pins
- Spread Bypass option available
- Industrial temperature range available
- For PCIe Gen2 applications, see the 5V41066
- For PCIe Gen3 applications, see the 5V41236
557-05A - Block Diagram
Description
The 557-05A is a spread-spectrum clock generator that supports PCI-Express requirements. It is used in PC or embedded systems to substantially reduce electro-magnetic interference (EMI). The device provides four differential HCSL or LVDS high-frequency outputs with spread spectrum capability. The output frequency and spread type are selectable using external pins.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 4 |
| Diff. Output Signaling | HCSL |
| Output Freq Range (MHz) | 100 - 100, 200 - 200 |
| Power Consumption Typ (mW) | 396 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | HCSL |
| Xtal Freq (MHz) | 25 - 25 |
| Diff. Termination Resistors | 16 |
| Package Area (mm²) | 28.6 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TSSOP | 6.5 x 4.4 x 1.0 | 20 | 0.65 |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 557G-05ALF | Active | Available | In Stock | TSSOP | 1ku | $2.08 | 20# | Tube | 1 | 0 | 74# | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 557G-05ALFT | Active | N/A | In Stock | TSSOP | 1ku | $2.08 | 20# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 557GI-05ALF | Active | Available | In Stock | TSSOP | 1ku | $2.24 | 20# | Tube | 1 | 0 | 74# | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
| 557GI-05ALFT | Active | N/A | In Stock | TSSOP | 1ku | $2.24 | 20# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (14)
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- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
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- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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