Features
- Ultra-low phase noise synthesizer: Jitter below 18fs RMS from 12kHz to 20MHz with a 4MHz high-pass filter (HPF)
- Independent synchronization domains: Two independent low phase noise synchronization domains
- Frequency domains: Four independent low phase noise frequency domains
- Clock outputs: Eight clock outputs with independent integer dividers
- Six outputs configurable as LVDS, HCSL (AC-LVPECL), or CML
- Two outputs configurable as LVDS, HCSL (AC-LVPECL), or LVCMOS
- Output frequency range
- CML: DC to 2.5GHz
- LVDS or HCSL: DC to 1GHz
- LVCMOS: DC to 250MHz
- Clock inputs: Two differential clock inputs configurable as four single-ended inputs
- Power requirements
- Operates from a 1.8V supply
- Clock inputs tolerate a 1.8V input when the device is powered off, sinking less than 1mA
- Input frequency range: CLKIN input frequency range: DC to 1GHz
- Time sync TDC: Supports 1PPS (one pulse per second) and PP2S inputs
- Digital phase-locked loops (DPLLs)
- Comply with ITU-T G.8262 and G.8262.1
- Input-to-output phase variation ≤ 100ps
- Digitally controlled oscillator (DCO): Frequency resolution < 10^-13
- Physical package: 7mm × 7mm, 64-pin BGA
Description
The RC38208 is a high-performance, small form factor, low-power jitter attenuator, multi-frequency clock synthesizer, and digitally controlled oscillator (DCO) designed for critical applications such as 4G/5G RF transceivers and high-speed SerDes. It belongs to Renesas' high-performance FemtoClock™ 3 wireless family. It generates clocks with ultra-low in-band phase noise and spurious signals, achieving jitter below 18fs RMS, making it ideal for 112Gbps and 224Gbps SerDes. The RC38208 can manage up to three synchronization domains, supporting CPRI/eCPRI and synchronization methods like IEEE 1588, Synchronous Ethernet (SyncE), GPI, or GNSS. With up to four frequency domains, it simplifies system clock generation, while integrated LDOs provide superior PSRR, reducing PCB complexity. This makes it an excellent choice for applications such as timing for optical front-end DAC/ADC and DSP, reference clocks for high-speed SerDes, 5G distribution units, and high-performance DCO for PTP-based clocks.
Parameters
| Attributes | Value |
|---|---|
| Wireless | 1 |
| Inputs (#) | 4 |
| Input Type | CML, Crystal, HCSL, LVCMOS, LVDS, LVPECL |
| Product Category | FemtoClock 3, Jitter Attenuators |
| Output Type | HCSL, LVCMOS, LVDS |
| Output Voltage (V) | 1.8 |
| Input Freq (MHz) | 5.0E-7 - 1000 |
| Phase Jitter Typ RMS (ps) | 0.018 |
| Output Freq Range (MHz) | 5.0E-7 - 1000 |
| Core Voltage (V) | 1.8V, 3.3V |
| Output Banks (#) | 8 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| CABGA | 7.0 x 7.0 x 1.09 | 64 | 0.8 |
Applications
- Timing for optical front-end DAC/ADC and DSP
- Reference clock for 112Gbps and 224Gbps SerDes
- 5G distribution units (DU), switches, and routers
- High-performance DCO for precision time protocol (PTP) based clocks
Renesas Boards & Kits
FemtoClock 3 Wireless Ultra-Low Phase Noise Synchronizer and Jitter Attenuator Evaluation Kit
This RC38208A evaluation kit is used to evaluate the RC38208 FemtoClock™ 3 ultra-low phase noise jitter attenuator and clock generator. The RC38208 and RC38108 are ultra-low phase noise jitter attenuators, multi-frequency clock synthesizers, and digitally controlled oscillators (DCO). This... Read More
Knowledge Base
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How to configure Direct-Coupled HCSL termination on the RC32308A or RC32312A?
For HCSL receivers, RC38208/RC38108 clock outputs should be configured for HCSL, and the devices should be directly coupled. The RC38208/RC38108 supports several programmable HCSL voltage swing options. Figure 10 shows an HCSL driver directly coupled with an HCSL receiver and configured for internal source termination. The ...
Apr 18, 2024 -
How do I configure AC-Coupled Differential Termination on the RC32308A or RC32312A?
For AC-coupled differential terminations, the RC38208/RC38108 clock outputs should be configured for HCSL and the HCSL driver should be configured with a voltage swing appropriate for the receiver. The RC38208/RC38108 supports several programmable HCSL voltage swing options. AC-coupling should be used for LVPECL receivers ...
Apr 18, 2024 -
Does the RC32308A or the RC32312Asupport output clocks for LVDS, HCSL, or CML?
The RC38208/RC38108 programmable differential clock outputs support LVDS, HCSL, and CML. Receivers that support LVDS, HCSL, or CML can be directly coupled with RC38208/RC38108 outputs. Differential receiver types other than LVDS, HCSL, or CML can be AC-coupled. The RC38208 or RC38108 differential clock outputs support ...
Apr 18, 2024
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