RC32312A-EVK

This RC32312A-EVK evaluation kit is used to evaluate the RC32312A FemtoClock™ 3 jitter attenuator and clock generator. The RC32312A provides one independent timing channel that can be configured as digital PLLs (DPLLs) or as digitally controlled oscillators (DCOs) and with up to four independent frequency domains that are each either locked to the external reference input or locked to a free-run crystal or oscillator. The DPLL channels meet synchronous Ethernet clock requirements and they can be used for jitter attenuation and frequency translation. The DCOs can be programmed to synthesize the desired frequency and can be steered by external software with a resolution of 1.11^e-13. The DPLLs can lock to virtually any frequency from 4kHz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 4kHz to 1GHz with typical jitter below 65fs RMS from 12kHz to 20MHz in jitter attenuator mode and below 55fs RMS from 12kHz to 20MHz in clock generator mode.