The 8T73S1802 is a fully integrated clock fanout buffer and frequency divider. The input signal is frequency-divided and then fanned out to one differential LVPECL and one LVCMOS output. Each of the outputs can select its individual divider value from the range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level logic) are available to select the frequency dividers and the output enable/disable state. The single-ended LVCMOS output is phase-delayed by 650ps to minimize coupling of LVCMOS switching into the differential output during its signal transition.

The 8T73S1802 is optimized to deliver very low phase noise clocks. The VBB output generates a common-mode voltage reference for the differential clock input so that connecting the VBB pin to an unused input (nCLK) enables to use of single-ended input signals. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The device is a member of the high-performance clock family from IDT.

特長

  • High-performance fanout buffer clock and fanout buffer
  • Input clock signal is distributed to one LVPECL and one LVCMOS output
  • Configurable output dividers for both LVPECL and LVCMOS outputs
  • Supports clock frequencies up to 1000MHz (LVPECL) and up to 200MHz (LVCMOS)
  • Flexible differential input supports LVPECL, LVDS and CML
  • VBB generator output supports single-ended input signal applications
  • Optimized for low phase noise
  • 650ps delay between LVCMOS and LVPECL minimizes coupling between outputs
  • Supply voltage: 3.3V or 2.5V
  • -40°C to 85°C ambient operating temperature
  • 16 VFQFN package (3mm x 3mm)

製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8T73S1802NLGI
Active VFQFPN 16 I はい Tray
Availability
8T73S1802NLGI/W
Active VFQFPN 16 I はい Reel
Availability
8T73S1802NLGI8
Active VFQFPN 16 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8T73S1802 Datasheet データシート PDF 1.04 MB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PCN# : PCN200016 Change Shipping Media on Select Package 製品変更通知 PDF 2.97 MB
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
製品変更通知 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
製品変更通知 PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1809-04 Add Alternate Assembly Location for QFN packages 製品変更通知 PDF 36 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Products for Radio Applications (Japanese) English 製品概要 PDF 6.27 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

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