The 82P33910 Synchronization System for IEEE 1588 is comprised of software and hardware designed to meet the needs of IEEE 1588 slave clock and master clock applications. The system includes a clock recovery servo software (Servo) that runs on an external processor and Synchronization Management Unit (SMU) hardware. The Servo recovers accurate and stable electrical synchronization signals from packet based references generated by IEEE 1588 masters. The Servo is capable of filtering the effects of Packet Delay Variation (PDV) often present in IEEE 1588 unaware networks.

The SMU hardware provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

The 82P33910-1 is no longer recommended for new designs. The only difference between the 82P33910-1 and the 82P33910 is that the 82P33910-1 relied on a proprietary PTP stack, whereas the 82P33910 relies on the Linux PTP stack, which is open source.

For more information or to request documentation, please contact your local Renesas sales representative.

特長

  • Includes clock recovery servo software, and Synchronization Management Unit (SMU) hardware
  • Implements ITU-T Telecom Profiles
  • Operates as IEEE 1588 / PTP slave or master
  • Recovers accurate and stable synchronization signals from packet based IEEE 1588 / PTP master
  • Reference trackers filter packet synchronization noise from IEEE 1588 unaware networks
  • PTP clocks comply with ITU-T G8273.2 and G.8263
  • Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • System-wide precise 1PPS (Pulse Per Second) time of day alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • 144 pin CABGA package

tune製品選択

製品名 Part Status Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active C はい Tray
Availability
Active C はい Reel
Availability

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
データシート
star 82P33910 Datasheet データシート PDF 137 KB
ユーザーガイド、マニュアル
PTP Stack and Clock Manager Integration Guide ガイド PDF 980 KB
PTP Stack and Clock Manager Software Reference Manual ガイド PDF 2.28 MB
Timing Commander Installation Guide ガイド PDF 497 KB
アプリケーションノート、ホワイトペーパー
AN-888 SMU for IEEE 1588 and Synchronous Ethernet 82P338xx/339xx Register Map アプリケーションノート PDF 1.59 MB
AN-807 Recommended Crystal Oscillators for Network Synchronization アプリケーションノート PDF 148 KB
Procedure to Program Clock Phase Skew of 82P338XX_9XX_r6 アプリケーションノート PDF 755 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment アプリケーションノート PDF 324 KB
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx アプリケーションノート PDF 249 KB
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs アプリケーションノート PDF 606 KB
ITU-T Profiles for IEEE 1588 ホワイトペーパー PDF 1.17 MB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations アプリケーションノート PDF 115 KB
AN-839 RMS Phase Jitter アプリケーションノート PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
AN-806 Power Supply Noise Rejection アプリケーションノート PDF 438 KB
PCN / PDN
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages 製品変更通知 PDF 93 KB
その他資料
Timing Fabric for Next Generation Communications Equipment Overview (Japanese) English, 简体中文 概要 PDF 1.31 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
Timing Fabric for Communications Equipment Overview 概要 PDF 263 KB

file_downloadダウンロード

タイトル language 分類 形式 サイズ 日付
ソフトウェア
Timing Commander Installer (v1.16.4) ソフトウェア/ツール-その他 ZIP 19.79 MB
モデル
82P33910-1 BSDL File モデル-BSDL BSD 21 KB