The HD-6402 is a CMOS UART for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code. The HD-6402 can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. Utilizing the Intersil advanced scaled SAJI IV CMOS process permits operation clock frequencies up to 8. 0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface.
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|PDF 322 KB||Datasheet|
|PDF 338 KB||Application Note|
|PDF 467 KB||Brochure|
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|PDF 282 KB||Product Advisory|
|PDF 323 KB||Product Change Notice|
|PDF 174 KB||Product Change Notice|
PCN11040 - Manufacturing Site Change for Assembly of Intersil Ceramic Dual-In-Line (Frit Seal Cerdip) Products - Amkor (ATP) Muntinlupa City, PhilippinesPDF 151 KB
|Product Change Notice|
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