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Features

  • Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Bidirectional data inputs and outputs directly LVTTL-compatible
  • Low power consumption via chip deselect
  • Upper and Lower Byte Enable Pins
  • Single 3.3V power supply
  • Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages

Description

The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.

Parameters

Attributes Value
Density (Kb) 1024
Bus Width (bits) 16
Core Voltage (V) 3.3
Organization 64K x 16
I/O Voltage (V) -
Access Time (ns) 10, 12, 15, 20
Temp. Range (°C) -40 to 85°C, 0 to 70°C
Architecture Asynchronous

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
CABGA 7.0 x 7.0 x 1.4 48 0.75
TSOP 18.41 x 10.16 x 1.0 44 0.8

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