Overview

Description

The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.

Features

  • Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Bidirectional data inputs and outputs directly LVTTL-compatible
  • Low power consumption via chip deselect
  • Upper and Lower Byte Enable Pins
  • Single 3.3V power supply
  • Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages

Documentation

Type
Date
PDF 108 KB Datasheet
PDF 471 KB 日本語 Guide
PDF 1.11 MB End Of Life Notice
PDF 1.27 MB 日本語 Guide
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PDF 909 KB End Of Life Notice
PDF 155 KB Product Change Notice
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PDF 748 KB Product Change Notice
PDF 108 KB Product Change Notice
PDF 24 KB Product Change Notice
PDF 248 KB End Of Life Notice
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PDF 117 KB Product Change Notice
PDF 115 KB Product Change Notice
PDF 729 KB Product Change Notice
PDF 18 KB Product Change Notice
PDF 38 KB Product Change Notice
PDF 16 KB Product Change Notice
PDF 290 KB Product Change Notice
PDF 47 KB Product Change Notice
PDF 35 KB Product Change Notice
PDF 80 KB Product Change Notice
PDF 38 KB Product Change Notice
PDF 18 KB Product Change Notice
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PDF 125 KB Product Change Notice
PDF 423 KB Product Change Notice
PDF 48 KB Product Change Notice
PDF 40 KB Product Change Notice
PDF 274 KB Product Change Notice
PDF 15 KB End Of Life Notice
PDF 11 KB Product Change Notice
PDF 20 KB Product Change Notice
PDF 44 KB Product Change Notice
35 items

Design & Development

Software & Tools

Software Downloads

Type Date
PDF 1.11 MB End Of Life Notice
PDF 938 KB End Of Life Notice
PDF 909 KB End Of Life Notice
PDF 248 KB End Of Life Notice
PDF 15 KB End Of Life Notice
5 items

Models

Models

Type Date
ZIP 13 KB Model - IBIS
1 item

Support