Overview

Description

The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.

Features

  • Equal access and cycle times — Commercial: 10/12/15/20ns — Industrial: 12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Bidirectional data inputs and outputs directly LVTTL-compatible
  • Low power consumption via chip deselect
  • Upper and Lower Byte Enable Pins
  • Single 3.3V power supply
  • Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages

Comparison

Applications

Documentation

Design & Development

Models

Support