Overview
Description
The 2510C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The 2510C operates at 3.3V VCC and drives up to ten clock loads.
Features
- Meets or exceeds PC133 registered DIMM specification1.1
- Spread Spectrum Clock Compatible
- Distributes one clock input to one bank of ten outputs
- Operating frequency 25MHz to 175MHz
- External feedback input (FBIN) terminal is used to synchronize the outputs to the clock input
- No external RC network required
- Operates at 3.3V Vcc
- Plastic 24-pin 173mil TSSOP package
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 214 KB | |
| Product Change Notice | PDF 611 KB | |
| Product Change Notice | PDF 611 KB | |
| Product Change Notice | PDF 95 KB | |
| Product Change Notice | PDF 50 KB | |
| Product Change Notice | PDF 361 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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