The M66291 is a device controller, compliant with the Full-Speed USB2.0, and featuring the Full-Speed transfer mode. It comes with a USB transceiver circuit and supports all transfer types. The M66291 includes a built-in 3K-byte FIFO and offers up to seven endpoints. The M66291 supports various DMA modes owing to the built-in DMA interface (2-ch) and selectable polarity. In addition, the M66291 comes equipped with two interrupt pins, with selectable polarity and interrupt source options, connection to CPU of 5V power supply is available because the I/O power supply is 2.7V to 5.5V.

The M66291 is developed with Renesas' original, widely used Full-Speed USB IP, ensuring smooth upgrades to system LSIs for further developments. For evaluation tools of this group, please refer to "Software and Tools".

Note: Although "USB specification 1.1 compliant" is written in the M66291GP datasheet, the M66291 is also USB specification 2.0 compliant.

Applications

  • Printer, scanner, DSC, DVC
  • PC camera, multimedia speaker, terminal adapter, etc.
  • Support all PC peripheral using Full Speed USB

descriptionDocumentation

Title language Type Format File Size Date
star M66291 Datasheet 日本語 Datasheet PDF 928 KB
USB ASSP Evaluation MotherBoard M3A-0033 Manual 日本語 Manual - Development Tools PDF 797 KB
star M66291GP Utility Board M3A-0032 Instruction Manual 日本語 Manual - Development Tools PDF 306 KB
Converter Board for USB ASSP Utility Board M3A-ZA53 日本語 Manual - Development Tools PDF 391 KB
M66291 Usage Precautions of the Buffer memory initialization by the Control Read Buffer 日本語 Technical Update PDF 25 KB
M66291 Control transfer status stage transition interrupt Limitations Technical Update PDF 20 KB
M66291 Control Read Transfer Limitations Technical Update PDF 20 KB
M66291/M66290 Receive Data Length Limitations Technical Update PDF 55 KB
TECHNICAL NEWS M66291 *TC1 Pin Usage Limitations Technical Update PDF 43 KB
TECHNICAL NEWS M66291 D1_FIFO Access: Read Signal Timing Requirements Technical Update PDF 43 KB
TECHNICAL NEWS M66291 Dn_FIFO Usage Limitations Technical Update PDF 58 KB
TECHNICAL NEWS M66291 Dreq Signal Assertion Limitation Technical Update PDF 52 KB
TECHNICAL NEWS M66291 IN-Direction DMA Transfer Limitations Technical Update PDF 71 KB
TECHNICAL NEWS M66291 Oscillator Limitations Technical Update PDF 41 KB

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