The 8V19N492-39 is a fully integrated FemtoClock NG Jitter Attenuator and Clock Synthesizer that is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, LTE-A and 5G radio board implementations.

The device supports JESD204B/C subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.

The 8V19N492-39 supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through a selectable 3/4-wire SPI interface and reports lock and signal loss status in internal registers and via an lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The 8V19N492-39 is ideal for driving converter circuits in wireless infrastructure, radar/imaging and instrumentation/medical applications.

For information regarding evaluation boards and material, please contact your local sales representative.


  • High-performance clock RF-PLL with support for JESD204B/C
  • Optimized for low phase noise: -150.5dBc/Hz (800kHz offset), 245.76MHz clock
  • Integrated phase noise of 46fs RMS typical (12kHz–20MHz)
  • Dual-PLL architecture
  • First PLL stage with external VCXO for clock jitter attenuation
  • Second PLL with internal FemtoClockNG PLL: 3932.16MHz
  • Five output channels with a total of 15 outputs
  • Configurable integer clock frequency dividers
  • Low-power LVPECL/LVDS outputs support configurable signal amplitude, DC and AC coupling, and LVPECL, LVDS line terminations techniques
  • Phase delay circuits
  • Redundant input clock architecture with two inputs
  • SYSREF generation modes include internal and external trigger mode for JESD204B/C
  • Supply voltage: 3.3V
  • SPI interface, 3/4 wire configurable

Product Options

Part Number Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active IDTDUMMY00 VFQFPN 88 I Yes Tray
Active IDTDUMMY00 VFQFPN 88 I Yes Reel


Title language Type Format File Size Date
Datasheets & Errata
8V19N492-39 Datasheet Datasheet PDF 1.94 MB
User Guides & Manuals
8V19N49x Hardware Design Guide Guide PDF 947 KB
Application Notes & White Papers
AN-952 8V19N480_490 Design Guide for JESD204B Output Phase Alignment and Termination Application Note PDF 975 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
8V19N49x RF Sampling Clocks with Jitter Attenuation Overview Overview PDF 1.21 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB


Title language Type Format File Size Date
8V19N480-490 Timing Commander Personality File (v5.1.0) Software ZIP 4.59 MB

Boards & Kits

Part Number Title Type Company
8V19N492-39-EVK Evaluation Board for 8V19N492-39 Evaluation Renesas