Intersil's R4TM Control Loop: Industry-Leading Transient Response
Hi, my name is Brandon Howell and I'm the Product Marketing Manager for Intersil's digital power products. In this video, we'll be looking at the R4 modulator found in our new family of ISL68200 and ISL68201 hybrid digital controllers.
Intersil's R4 control loop is based on a current mode hysteretic control. The loop is inherently stable with digitally adjustable gain through the optional PMBus interface found on the ISL68200 and ISL68201. The main benefits of this control loop include high control loop bandwidth, inherently stable architecture, the ability to adjust both switching frequency and duty cycle in response to a load transient and the seamless PFM to PWM transition for excellent light-load efficiency.
To really showcase the R4 modulator, we did a comparison with the voltage mode control loop and a constant on-time control loop, two very popular control loops in the market place. For this comparison, we did a 12V input to a 1V output, a 500kHz switching frequency, same inductor, and same all-ceramic output capacitance filter. The same load was used to provide a 12A load step at 25A/ms. The only difference between the setups was the control loop, R4 versus voltage mode versus constant on-time.
If you examine the architecture of a voltage mode control loop, it consists of an error amplifier, a comparator, and a digital latch that is used to generate the PWM pulse to drive the power stage. The main takeaway on this slide is that voltage mode control is a fixed frequency variable duty cycle architecture. And it requires compensation around the amplifier which the end-user must typically set up.
Here, we're showcasing the transient response of a voltage mode controller with a 12A load step applied. Channel 1 is the output voltage, Channel 3 is the switch node, and Channel 2 is the load step that's been applied. With the load step, the upper voltage deviates by about 4.5%. There's a 2µs delay until the control loop can respond to the load step due to the compensation around the error amplifier.
On the load release side, VL deviates by approximately 5%. Again, there's about a 2µs delay until the controller can respond to the load transient because of the compensation around the error amplifier.
On this slide, we are showing the architecture of a constant on-time control loop. A constant on-time control loop consists of comparator and on-time generator. When the feedback voltage is lower than the reference the on-time generator is triggered and a fixed pulse width signal is sent to the power stage. So constant on-time is a variable frequency with fixed duty cycle modulator.
Here, we are showing a similar scope shot for a constant on-time modulator. Channel 1 is the output voltage, Channel 3 is the switch node, and Channel 2 is the load step. For constant on-time architecture when a load step is applied, the switching frequency temporarily increases but the duty cycle remains fixed. It performs better than the voltage mode controller with a 3.5% deviation for a load step and approximately a 3.7% deviation for the load release.
On this slide, we show the R4 control loop. This is Intersil's proprietary control loop, again, based on hysteretic current mode control. There's a feedback signal that gets compared to a reference, and that is used to generate a window voltage. Inside that window voltage, a synthetic ripple current is bounded using window comparators. When the synthetic ripple current has the lower comparator, the high-side FET is turned on. And when it hits the high-side comparator the high-side FET is turned off. This is used to generate the PWM signal that drives the power stage. This architecture offers a variable frequency and a variable duty cycle architecture.
This slide showcases the R4 transient response to the same load steps as the previous cases. Again, Channel 1 is the output voltage, Channel 3 is the switch node, and Channel 2 is the load step. Because R4 offers both variable frequency and variable duty cycle, the deviation in the output voltage is reduced to less than 1.4%. The load release is approximately the same for the constant on-time, and this is more a limitation of a buck regulator architecture.
In summary, the R4 control loop, because it's based on a variable frequency, variable duty cycle architecture, has one-half the peak-to-peak deviation with comparable conditions as a voltage mode controller and a constant on-time controller. This superior transient performance allows you to do a design with fewer off capacitors, which save both forward space and BOM cost.