ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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9ZXL0851E

アクティブ

8-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

ご購入

特長

  • LP-HCSL outputs with 85Ω Zout; eliminate 32 resistors, save 64mm² of area
  • PCIe Gen 1–5 compliance
  • 8 OE# pins; hardware control of each output
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz PLL mode; UPI and legacy QPI support
  • 6mm × 6mm 48-VFQFPN package; small board footprint
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9ZXL04x1-06x1-08x1-12x1 - Block Diagram
9ZXL0851E - Pinout
9ZXL04x1-06x1-08x1-12x1 - Block Diagram
9ZXL0851E - Pinout

説明

The 9ZXL0851E is a second-generation enhanced performance DB800ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL0851A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.

パラメータ

属性 値
Chipset Manufacturer Intel
Clock Spec. DB800ZL v1.2 Derivative
Diff. Outputs 8
Diff. Output Signaling LP-HCSL
Output Enable (OE) Pins 8
Output Freq Range (MHz) 1 - 400
Diff. Inputs 1
Diff. Input Signaling HCSL
Accepts Spread Spec Input Yes
Power Consumption Typ (mW) 304
App Jitter Compliance PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, QPI, UPI, 25G EDR, IF-UPI, PCIe Gen5, DB2000Q
Package Area (mm²) 81

パッケージオプション

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 6.0 x 6.0 x 0.9 48 0.4

アプリケーション

  • Servers/High-performance Computing
  • nVME Storage
  • Networking
  • Accelerators
  • Industrial Control

適用されたフィルター

読込中
読込中

Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

読込中 読込中