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8SLVD2104

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Product Longevity: 2040

Dual 1:4, LVDS Output Fanout Buffer

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Features

  • Two 1:4, low skew, low additive jitter LVDS fanout buffers
  • Two differential clock inputs
  • Differential pairs can accept the following differential input levels: LVDS and LVPECL
  • Maximum input clock frequency: 2GHz
  • Output bank skew: 35ps, (maximum)
  • Propagation delay: 300ps, (maximum)
  • Low additive RMS phase jitter, 156.25MHz (10kHz to 20MHz): 105fs, (maximum)
  • 2.5V supply voltage
  • Lead-free (RoHS 6) 28-lead VFQFN package
  • -40 °C to 85 °C ambient operating temperature
Find Other Products in RF Buffers
8SLVD2104 - Block Diagram
8SLVD2104 - Pin Assignment
8SLVD2104 - Block Diagram
8SLVD2104 - Pin Assignment

Description

The 8SLVD2104 is a high-performance differential dual 1:4 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2104 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2104 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with four low-skew outputs each are available. The integrated bias voltage generators enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Parameters

Attributes Value
Outputs (#) 8
Inputs (#) 2
Channels (#) 2
Input Freq (MHz) 2000
Output Freq Range (MHz) 2000
Output Skew (ps) 35
Adjustable Phase No
Noise Floor (dBc/Hz) -160
Additive Phase Jitter Typ RMS (fs) 105
Output Type LVDS
Supply Voltage (V) 2.5 - 2.5
Advanced Features Dual Buffer

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 5.0 x 5.0 x 0.8 28 0.5

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Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit Renesas's RF Buffer page.

 

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