概要
説明
The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique.
特長
- 10 ns read/write cycle time
- Empty and Full flags signal FIFO status
- Easy expandable in depth and width
- Asynchronous or coincident read and write clocks
- Programmable Almost-Empty and Almost-Full flags with default settings
- Half-Full flag capability
- Dual-Port zero fall-through time architecture
- Output enable puts output data bus in high-impedance state
- Available in 64-pin TQFP, STQFP and 68-pin PLCC packages
- Industrial temperature range (–40C to +85C) is available
ドキュメント
| Document title | Document type
|
日付 日付 | |
|---|---|---|---|
| PDF 205 KB | データシート | ||
| PDF 125 KB | アプリケーションノート | ||
| PDF 334 KB | アプリケーションノート | ||
| PDF 645 KB | EOL通知 | ||
| PDF 123 KB | ガイド | ||
| PDF 95 KB | 製品変更通知 | ||
| PDF 50 KB | 製品変更通知 | ||
| PDF 129 KB | 製品変更通知 | ||
| PDF 24 KB | 製品変更通知 | ||
| PDF 252 KB | 製品変更通知 | ||
| PDF 223 KB | 製品変更通知 | ||
| PDF 164 KB | 製品変更通知 | ||
| PDF 729 KB | 製品変更通知 | ||
| PDF 290 KB | 製品変更通知 | ||
| PDF 80 KB | 製品変更通知 | ||
| PDF 26 KB | 製品変更通知 | ||
| PDF 134 KB | 製品変更通知 | ||
| PDF 150 KB | 製品変更通知 | ||
| PDF 65 KB | 製品変更通知 | ||
| PDF 150 KB | 製品変更通知 | ||
| PDF 49 KB | 製品変更通知 | ||
| PDF 48 KB | 製品変更通知 | ||
| PDF 40 KB | 製品変更通知 | ||
| PDF 274 KB | 製品変更通知 | ||
| PDF 44 KB | 製品変更通知 | ||
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製品選択
Processing table
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
ご購入 / サンプル |
|
|---|---|---|---|---|---|---|
| 型名 | ||||||
| TQFP | 64 | C | Yes | Tray | サンプルを入手, | |
| TQFP | 64 | C | Yes | Reel |
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