特長

• Jitter below 100fs RMS (10kHz to 20MHz)
• Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
• PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
  • Operates from an internal crystal
  • APLL frequency independent of input/crystal frequency
  • Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO)
  • DPLL loop filter programmable from 0.1Hz to 12kHz
  • DCO has tuning granularity of < 1ppb
• Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
  • Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS)
  • Reference monitor qualifies/disqualifies input clock
• Programmable status output
• 4 differential/8 LVCMOS outputs
  • Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
  • Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS
  • Differential output swing is selectable: 400mV to 800mV
  • Output clock phase individually adjustable in 100ps steps
  • Output Enable input with programmable effect
• Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
• Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
• 4 × 4 mm 28-VFQFPN package