特長
- One differential HSTL output pair
One differential feedback output pair - Differential CLK, nCLK input pair
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, and SSTL
- Output frequency range: 31.25MHz to 630MHz
- Input frequency range: 31.25MHz to 630MHz
- VCO range: 250MHz to 630MHz
- External feedback for “zero delay” clock regeneration with configurable frequencies
- Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
- Cycle-to-Cycle jitter: 50ps (maximum)
- Output skew: 50ps (maximum)
- Static phase offset: 200ps (maximum)
- 3.3V core, 1.8V output operating supply
- 0 °C to 70 °C ambient operating temperature
説明
The 8725B-21 is a highly versatile 1:1 differential-to-HSTL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The 8725B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier, or divider, and has an output frequency range of 31.25MHz to 630MHz. The reference divider, feedback divider, and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.