概要
説明
The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec.
特長
- Low additive phase jitter RMS: 50fs
- Extremely low skew outputs (50ps)
- Low cost clock buffer
- Packaged in 8-SOIC and 8-DFN, Pb-free
- ICLK is PDT and may be driven before VDD is applied
- Direct-coupled signal path suitable for 1pps clocks
- Input / Output clock frequency up to 200MHz
- Non-inverting output clock
- Ideal for networking clocks
- Operating voltages: 1.8V to 3.3V
- Advanced, low power CMOS process
- Extended temperature range (-40°C to +105°C)
ドキュメント
| Document title | Document type
|
日付 日付 | |
|---|---|---|---|
| PDF 267 KB | データシート | ||
| PDF 146 KB | アプリケーションノート | ||
| PDF 495 KB | アプリケーションノート | ||
| PDF 442 KB | アプリケーションノート | ||
| PDF 565 KB | アプリケーションノート | ||
| PDF 217 KB | 概要 | ||
| PDF 1.83 MB | 概要 | ||
| PDF 268 KB | 製品変更通知 | ||
| PDF 611 KB | 製品変更通知 | ||
| PDF 611 KB | 製品変更通知 | ||
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設計・開発
モデル
ECADモデル
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製品選択
Processing table
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play_circle_filledビデオ&トレーニング
Low-jitter LVCMOS Fanout Clock Buffers by IDT
Video List