20-Output Enhanced DB2000QL PCIe Clock Buffer
ページセクションへ移動：
概要
説明
The 9QXL2001C is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen1 to Gen6 applications. The 9QXL2001C provides two methods to control output enables; standard OE# pins and SMBus enable bits, and a simple 3-wire serial interface (Side-Band Interface) that is independent of the SMBus. The Side-Band Interface is enabled via a hardware strap and operates simultaneously with the OE# pins and SMBus enable bits. It offers integrated terminations for 85Ω transmission lines.
特長
- 8 OE# pins provide hardware control of 8 outputs
- 20 SMBus bits allow software control of each output
- 3-wire Side-Band Interface provides serial control of all 20 outputs at 25MHz rate
- Outputs remain Low/Low when powered up with floating input clock
- Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
- Zo = 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
- 9 selectable SMBus addresses
- Spread spectrum compatible
- 6 × 6 mm dual-row 80-GQFN
ドキュメント
| Document title | Document type
|
日付 日付 | |
|---|---|---|---|
| PDF 547 KB | データシート | ||
| PDF 53 KB | 回路図 | ||
| PDF 91 KB | アプリケーションノート | ||
| PDF 1.99 MB | アプリケーションノート | ||
| PDF 255 KB | アプリケーションノート | ||
| PDF 322 KB | アプリケーションノート | ||
| PDF 480 KB | アプリケーションノート | ||
| PDF 235 KB | アプリケーションノート | ||
| PDF 170 KB | アプリケーションノート | ||
| PDF 495 KB | アプリケーションノート | ||
| PDF 442 KB | アプリケーションノート | ||
| PDF 160 KB | アプリケーションノート | ||
| PDF 120 KB | アプリケーションノート | ||
| PDF 565 KB | アプリケーションノート | ||
| PDF 137 KB | アプリケーションノート | ||
| PDF 2.40 MB | 概要 | ||
| PDF 1.83 MB | 概要 | ||
| PDF 100 KB | 製品変更通知 | ||
18 items
|
|||
設計・開発
モデル
ECADモデル
[製品選択]テーブル内の製品名をクリックするとSamacSysが提供する回路図シンボル、PCBフットプリント、3D CADモデルがご確認いただけます。 お探しのシンボルやモデルが見つからない場合、Webサイトから直接リクエストできます。
製品選択
Processing table
| VFQFPN | 80 | -40 to 105°C | Yes | Tray | ||
| VFQFPN | 80 | -40 to 105°C | Yes | Reel |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
play_circle_filledビデオ&トレーニング
PCIe Gen5 Clock Buffers
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.
Video List