The 9QXL2001C is a 20-output very-low additive phase jitter fanout buffer for PCIe Gen1 to Gen6 applications. The 9QXL2001C provides two methods to control output enables; standard OE# pins and SMBus enable bits, and a simple 3-wire serial interface (side-band interface) that is independent of the SMBus. The side-band interface is enabled via a hardware strap and operates simultaneously with the OE# pins and SMBus enable bits. It offers integrated terminations for 85Ω transmission lines.
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Pkg. Type |
Lead Count (#) |
Temp. Range |
Pb (Lead) Free |
Carrier Type |
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Price (USD) | 1ku |
ご購入 / サンプル |
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VFQFPN | 80 | -40 to 105°C | Yes | Tray | 3 | 3.719 | サンプルを入手, | |
VFQFPN | 80 | -40 to 105°C | Yes | Reel | 3 |
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.