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特長

  • PCIe Gen 1–6 CC-compliant
  • Supports PCIe SRIS and SRNS clocking
  • Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
  • Pin-selectable SRNS 0%, CC 0%, and CC/SRIS -0.5% spread
  • SMBus-selectable CC/SRIS -0.25% spread
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
  • Easy AC coupling to other logic families, see application note AN-891.
  • Space saving 4mm × 4mm 24-VFQFPN

説明

The 9FGL0241/51 devices are 2-output 3.3V PCIe Gen 1–6 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0241/51 supports PCIe Gen 1–6 Common Clocked architectures (CC), PCIe Separate Reference no Spread (SRNS), and Separate Reference Independent Spread (SRIS) clocking architectures.

パラメータ

属性
Temp. Range (°C) -40 to 85°C

パッケージオプション

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 4.0 x 4.0 x 0.9 24 0.5

アプリケーション

  • Servers/High-Performance Computing
  • nVME Storage
  • Networking
  • Accelerators
  • Industrial Control

適用されたフィルター

Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

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