パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | SOICW |
| Pkg. Code: | MWC |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 0.00 x 0.00 x 0.00 |
| Pitch (mm): |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 3 |
| RoHS (X28HC256SIZ-90) | ダウンロード |
| Pb (Lead) Free | Yes |
| ECCN (US) | |
| HTS (US) |
製品スペック
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 3 |
| Access Time (ns) | 90 |
| Family Name | Byte Alterable EEPROM |
| Interface | Parallel |
| Lead Count (#) | 28 |
| MOQ | 200 |
| Memory Capacity (kbit) | 256 |
| Organization (bit) | x 8 |
| Organization (kword) | 32 |
| Pb (Lead) Free | Yes |
| Pb Free Category | Pb-Free 100% Matte Tin Plate w/Anneal-e3 |
| Pkg. Dimensions (mm) | 0.0 x 0.0 x 0.00 |
| Pkg. Type | SOICW |
| Supply Voltage (V) | 4.5 - 5.5 |
| Temp. Range (°C) | -40 to +85°C |
X28HC256 に関するリソース
説明
The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24μs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0. 8s. The X28HC256 also features DATA polling and Toggle bit polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard software data protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 100, 000 write cycles per byte and an inherent data retention of 100 years