特長
- 1:12 PLL based low-voltage clock generator
- 3.3 V power supply
- Internal power-on reset
- Generates clock signals up to 242.5 MHz
- Maximum output skew of 250 ps
- Differential PECL reference clock input
- Two LVCMOS PLL reference clock inputs
- External PLL feedback supports zero-delay capability
- Various feedback and output dividers (refer to Application Section)
- Supports up to three individual generated output clock frequencies
- Synchronous output clock stop circuitry for each individual output for powerdown support
- Drives up to 24 clock lines
- Ambient temperature range -40°C to +85°C
- Pin and function compatible to the MPC973
- 52-lead Pb-free package available
説明
The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a nonbinary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers, bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9773. The MPC9773 has an internal power-on reset. The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
