特長
- Fully Integrated PLL
- Up to 200MHz I/O Frequency
- LVCMOS Outputs
- Outputs Disable in High Impedance
- LVPECL Reference Clock Options
- LQFP Packaging
- ±50ps Cycle–Cycle Jitter
- 150ps Output Skews
説明
The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.