特長
- Configurable 16 outputs LVCMOS clock distribution buffer
- Compatible to single, dual and mixed 3.3 V / 2.5 V voltage supply
- Output clock frequency up to 350 MHz
- Designed for high-performance telecom, networking and computer applications
- Supports applications requiring clock redundancy
- Maximum output skew of 250 ps (125 ps within one bank)
- Selectable output configurations per output bank
- Individually per-bank high-impedance tristate
- Output disable (stop in logic low state) control
- 48-lead LQFP package
- 48-lead Pb-free Package Available
- Ambient operating temperature range of –40 to 85°C
説明
The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the four output banks. Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individually supplied by 2.5 V or 3.3 V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in high-impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see Table 4. Output High-Impedance Control (OEN) for details. The outputs can be synchronously stopped (logic low state). The outputs provide LVCMOS compatible levels with the capability to drive terminated 50 ? transmission lines. For series terminated transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC = 3.3 V. The device is packaged in a 7x7 mm2 48-lead LQFP package.
