パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | TQFP |
| Pkg. Code: | PRG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 1.4 |
| Pitch (mm): | 0.8 |
環境及び輸出分類情報
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
製品スペック
| Pkg. Type | TQFP |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| C-C Jitter Max P-P (ps) | 300 |
| C-C Jitter Typ P-P (ps) | 100 |
| Core Voltage (V) | 3.3V, 2.5V |
| Divider Value | 2, 4, 8 |
| Feedback Divider | 16 - 16, 32 - 32 |
| Feedback Input | Yes |
| Input Freq (MHz) | 300 |
| Input Type | LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 2000 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 4 |
| Output Freq Range (MHz) | 25 - 200 |
| Output Signaling | LVCMOS |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3V, 2.5V |
| Outputs (#) | 9 |
| Package Area (mm²) | 49 |
| Pb Free Category | e3 Sn |
| Period Jitter Max P-P (ps) | 200 |
| Period Jitter Typ P-P (ps) | 80 |
| Phase Jitter Typ RMS (ps) | 20 |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 2000 |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1.4 |
| VCO Max Freq (MHz) | 400 |
| VCO Min Freq (MHz) | 200 |
| Width (mm) | 7 |
| Xtal Freq (KHz) | 25 |
| Xtal Inputs (#) | 1 |
MPC9350 に関するリソース
説明
The MPC9350 is a 2.5 V and 3.3 V compatible, PLL-based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 200 MHz and maximum output skews of 150 ps, the MPC9350 is ideal for the most demanding clock tree designs. The device offers 9 low skew clock outputs, with each one configurable to support the clocking needs of the various high-performance microprocessors, including the PowerQUICC II integrated communication microprocessor. The extended temperature range of the MPC9350 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter.