特長
- 4 differential LVPECL outputs
- 2 selectable LVCMOS/LVTTL inputs
- 1 GHz maximum output frequency
- Translates LVCMOS/LVTTL levels to LVPECL levels
- 30 ps maximum output skew
- 190 ps part-to-part skew
- 3.3 V operating range
- 20-lead TSSOP package
- Ambient temperature range –40°C to +85°C
- 20-lead Pb-free package available
MC100ES6535 - Block Diagram
説明
The MC100ES6535 is a low skew, high performance 3.3 V 1-to-4 LVCMOS to LVPECL fanout buffer. The ES6535 has two selectable inputs that allow LVCMOS or LVTTL input levels which translate to LVPECL outputs. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The ES6535 is ideal for high performance clock distribution applications.
