特長
- Quad 32Gbps linear TIA Integrated SPI and analog interface
- Differential linear gain: 150–5,000Ω, and > 30dB dynamic range
- 25+GHz adjustable 3dB bandwidth
- Automatic and manual gain control, Output Voltage Control, Peak Detection, RSSI and Input Current Monitor, and Shutdown functionalities
- Low THD, low cross-talk, and low power for covering 16QAM applications
GX32424 - Block Diagram
説明
The GX32424 is a 32Gbps linear quad TIA chip that integrates four lanes of TIAs for XI, XQ, YI, and YQ channels, as well as digital interface circuitry for DC controls on a single die for 100G/200G coherent applications.
The TIA electrical characteristics, functions, and physical dimensions are designed for a small-form factor integrated optical module such as CFP2 and CFP4.
パラメータ
| 属性 | 値 |
|---|---|
| Function | Linear TIA |
| Data Rate Max (Gbps) | 32 |
| Channels (#) | 4 |
パッケージオプション
| Pkg. Type |
|---|
| WAFER |
