ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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9DB833

アクティブ

8-Output 3.3V PCIe Gen1-2-3 Zero Delay/Fanout Buffer

ご購入
代替製品
9DBL0841 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DBL0851 - 8出力 3.3V PCIe ゼロ遅延／ファンアウトクロックバッファ
9ZXL0853E - 8-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

特長

  • Eight 0.7V HCSL differential output pairs
  • Phase jitter: PCIe Gen3 < 1ps rms
  • Phase jitter: PCIe Gen2 < 3.1ps rms
  • Phase jitter: PCIe Gen1 < 86ps peak-to-peak
  • Supports Zero Delay Buffer mode and Fanout mode
  • Bandwidth programming available
  • 3 selectable SMBus Addresses
  • 50MHz to 110MHz operation in PLL mode
  • 5MHz to 166MHz operation in Bypass mode
特定アプリケーション向けクロック内の他の製品を探す
9DB833 - Block Diagram
9DB833 - Pinout
9DB833 - Block Diagram
9DB833 - Pinout

説明

The 9DB833 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator.

パラメータ

属性値
Diff. Outputs8
Diff. Output SignalingHCSL
Output Freq Range (MHz)5 - 166.66
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)528
Supply Voltage (V)3.3 - 3.3
Output TypeHCSL
Diff. Termination Resistors32
Package Area (mm²)76.3
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)50 - 100
FunctionZero Delay Buffer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)3.3
Output Voltage (V)0.8

パッケージオプション

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
TSSOP12.5 x 6.1 x 1.0480.5

適用されたフィルター

読込中
読込中

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

読込中読込中