特長
- LP-HCSL outputs; up to 90% IO power reduction, better signal integrity over long traces
- Direct connect to 85Ω transmission lines; eliminates 60 termination resistors, saves 103mm² area
- Pin compatible with the 9ZXL1530; easy upgrade to reduced board space
- 64-VFQFPN package; smallest 15 output Z-buffer
- Fixed feedback path: ~ 0ps input-to-output delay
- 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
- Separate VDDIO for outputs; allows maximum power savings
- PLL or bypass mode; PLL can de-jitter incoming clock
- 100MHz and 133.33MHz PLL mode; legacy QPI/UPI support
- Selectable PLL BW; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- SMBus interface; unused outputs can be disabled
- 15 LP-HCSL Differential Output Pairs w/integrated terminations (Zo = 85Ω)
説明
The 9ZXL1550 is a DB1900Z derivative buffer utilizing Low-Power HCSL (LP-HCSL) outputs to increase edge rates on long traces, reduce board space, and reduce power consumption by more than 50% from the original 9ZX21501. It is pin-compatible with the 9ZXL1530 and has the output terminations integrated. It is suitable for PCI Express Gen 1/2/3 or QPI/UPI applications and uses fixed external feedback to maintain low drift for demanding QPI/UPI applications.
パラメータ
| 属性 | 値 |
|---|---|
| Chipset Manufacturer | Intel |
| Clock Spec. | DB1900Z v1.6 Derivative |
| Diff. Outputs | 15 |
| Diff. Output Signaling | LP-HCSL |
| Output Enable (OE) Pins | 0 |
| Output Freq Range (MHz) | 33 - 150 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 535 |
| Advanced Features | Multiple SMBus addresses, HW PLL mode control, SW PLL mode control |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, QPI |
| Package Area (mm²) | 81 |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 9.0 x 9.0 x 0.9 | 64 | 0.5 |