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特長

  • SMBus write lock pin, increases system security
  • PLL or Bypass mode; PLL can de-jitter incoming clock
  • PCIe Gen1–5 compliant in PLL mode
  • PCIe Gen1–5 compliant in Bypass mode
  • Supports PCIe SRIS and SRNS clocking
  • UPI/QPI support
  • LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
  • 12 OE# pins; hardware control of each output
  • Spread spectrum tolerant; allows reduction of EMI
  • 3 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Pin/SMBus selectable selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Easy AC coupling to other output logic like LVPECL/LVDS; see application note AN-891.
  • 10mm × 10mm 72-QFN package

説明

The 9ZML1256 is a second generation of enhanced performance DB1200ZL derivative. The device features both PLL and Bypass modes for flexibility. The PLL has a low noise PLL that can be used as a PCIe clock jitter cleaner. The device supports PCIe Gen1–5 and more complex architectures like SRIS and SRNS clocking.

For information regarding evaluation boards and material, please contact your local sales representative.

パラメータ

属性
Diff. Outputs12
Diff. Output SignalingLP-HCSL
Output Freq Range (MHz)1 - 400
Diff. Inputs2
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)343
Supply Voltage (V)3.3 - 3.3
Output TypeLP-HCSL
Diff. Termination Resistors0
Package Area (mm²)16
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)2
Input Freq (MHz)1 - 200
Additive Phase Jitter Typ RMS (fs)130
FunctionMultiplexer
Input TypeHCSL
Output Banks (#)1
Core Voltage (V)3.3
Output Voltage (V)0.4
Product CategoryClock Multiplexers, PCI Express Clocks, Processor Clock Buffers

パッケージオプション

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN10.0 x 10.0 x 1.0720.5

アプリケーション

  • Servers/High-performance Computing
  • nVME Storage
  • Networking
  • Accelerators
  • Industrial Control

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