パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG72 |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 72 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 168 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | TAIWAN |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 130 |
| Additive Phase Jitter Typ RMS (ps) | 0.13 |
| Advanced Features | Multiple SMBus addresses |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 |
| Architecture | Common, SRNS, SRIS |
| C-C Jitter Max P-P (ps) | 50 |
| Core Voltage (V) | 3.3V |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 2 |
| Diff. Output Signaling | LP-HCSL |
| Diff. Outputs | 12 |
| Diff. Termination Resistors | 0 |
| Feedback Input | No |
| Function | Multiplexer |
| Input Freq (MHz) | 1 - 200 |
| Input Type | HCSL |
| Inputs (#) | 2 |
| Length (mm) | 10 |
| MOQ | 168 |
| NXP Processor Function | SerDes Clock |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 1 - 400 |
| Output Impedance | 85 |
| Output Skew (ps) | 50 |
| Output Type | LP-HCSL |
| Output Voltage (V) | 0.4V |
| Outputs (#) | 12 |
| PLL | Yes |
| Package Area (mm²) | 16 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Power Consumption Typ (mW) | 343 |
| Price (USD) | $6.0875 |
| Prog. Clock | No |
| Reference Output | No |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
| 掲載 | No |
9ZML1255 に関するリソース
説明
The 9ZML1255 is a second generation of enhanced performance DB1200ZL derivative. The device features both PLL and Bypass modes for flexibility. The PLL has a low noise PLL that can be used as a PCIe clock jitter cleaner. The device supports PCIe Gen1–5 and more complex architectures like SRIS and SRNS clocking. 9ZML1255 also features an SMBus Write Lockout pin for increased device and system security.
For information regarding evaluation boards and material, please contact your local sales representative.