特長
- Additive PCIe Gen 5 CC jitter < 60fs RMS (fanout mode)
- PCIe Gen 5 CC jitter < 150fs RMS (High-BW Zero Delay Buffer (ZDB) mode)
- 6 low-power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
- Direct connection to 100Ω transmission lines
- Dedicated OE# pin for each output
- Spread spectrum tolerant
- Pin or SMBus configuration
- 3 selectable SMBus addresses
- SMBus interface not required for device operation
- Easy AC coupling to other logic families, see application note AN-891
- Space-saving 40-pin 5mm × 5mm VFQFPN
説明
The 9DBL0641 6-output zero-delay/fanout buffer is a 3.3V member of Renesas' full-featured PCIe family. The 9DBL0641 supports PCIe Gen 1 through Gen 5 and both Common and Independent Reference Clock architectures.
For information regarding evaluation boards and material, please contact your local sales representative.
パラメータ
| 属性 | 値 |
|---|---|
| Function | Zero Delay Buffer |
| Architecture | Common, SRNS, SRIS |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5 |
| Diff. Outputs | 6 |
| Diff. Output Signaling | LP-HCSL |
| Output Impedance | 100 |
| Diff. Inputs | 1 |
| Power Consumption Typ (mW) | 149 |
| Supply Voltage (V) | - |
| Advanced Features | Multiple SMBus addresses |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
アプリケーション
- PCIe Riser Cards
- nVME Storage
- Networking
- Accelerators
- Industrial Control/Embedded
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A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
TRANSCRIPT
Hi there. This is the first in the five-part series on IDT's new full-featured PCIe clock family. The first part in the series will be a family overview. There will also be a part on the clock generators, another section covering the clock buffers, a fourth section that will deal with the clock multiplexers and finally, a fifth section covering some of the applications for the full-featured PCIe clocks. So let's jump right into the family overview.
So PCI Express is evolving. There are two major things happening in PCI Express these days. One is the PCIe Gen4 specification is moving toward 0.9 drafts stage. And Gen4 is going to bring 16 Gbps data transfers to the architecture or to the PCI Express world. And then there's also going to be two new architectures which are supported in a non-specific way. The two architectures are the separate reference no spread--or SRNS--and the separate reference independence spread--or SRIS--clock architectures. These are going to be supported in the PCI Express Gen4 specification but there will be no explicit specifications on the reference clocks. So what the phrase is, is that SRNS and SRIS clocking will be implementation dependent. And what that means is that there's not gonna be an explicit reference clock jitter specification. And that means that IDT will need to work with the SOC vendors to ensure interoperability. And regardless of whether there's an explicit specification or not, IDT delivers solutions for these architectures and increasing performance requirements and we have always done so.
So in terms of the IDT's PCIe clock families, there are three major families. The focus of these series of presentations is on the full-featured PCIe, which you see on the left of your screen. We've just introduced the new L-series parts to production, which are the 3.3V devices that have the best performance - PCI Gen1 through 4, and also SRNS and SRIS support. And those follow the very successful 1.8V V-series and the 1.5V U-series parts which have been in the market for a couple of years supporting Gen1 through 3. The other specs and the Gen4 common clock spec are being evaluated against these parts to see if they will be able to do Gen4 or not. And so those other specs are TBD. The other family that we have is the PhiClock family, which is PhiClock plus PCIe in this case, where we add some less than 300 femtosecond RMS high-performance SerDes clocks or PhiClocks and then also provide some PCI Express Gen1 through 4 clocks.
Then the last family is when you really need to go smaller and you don't need all the features, you want a simpler board layout and you have very tight space constraints, is the micro-PCIe family which will be the subject of another presentation. And we're defining smaller as in micro-PCIe as any device that is in a 3x3 millimeter or smaller package.
So the common features of IDT's full-featured PCIe family are as follows. You have an Output Enable pin for every PCIe clock, you have Spread Spectrum Clocking capability and compatibility across every part in the family. On the clock generators, there is a reference output which can save you an XO in your system. And then to make it really simple to use the parts, you have--on the clock generators--you have pin control of three different spread amounts including spread off. And you also have on the zero-delay buffers pin control of the PLL bandwidth, whether you want it to be high bandwidth, low bandwidth or the PLL bypassed, that is all done from a single pin.
The other common feature is multiple, pin selectable SMBus addresses. So the clock generators have a choice of two SMBus addresses, the buffers have a choice of three SMBus addresses and those five addresses do not overlap. So you can have up to five of these devices on a single SMBus segment. The other common feature is that we use low power, and some people refer to this as push-pull, but we use low-power HCSL outputs on all the parts and they are offered with a choice of 100 ohm integrated terminations or 85 ohm integrated terminations. And all the parts in the full-featured family are between 2.5 mm x 2.5 mm up to 6 mm x 6 m. They all offer I-temp operation and the most power consuming part consumes 211 mW, so they are very power efficient.
So, the 3.3V full-featured PCIe clock family, which is the newest one, provides the basic functions you need for clocking, provides a clock generator function, provides both zero delay and fanout buffers, and provides a clock muxing function. And the muxes are two inputs with different numbers of outputs. In the 3.3V family, it's a 2-input and 4-output mux.
So the family has performance. The 3.3V family is PCIe Gen1, 2, 3, 4 common clocked compliant. It also supports the SRNS and SRIS architectures. You've got flexibility in the family where you can right-size the part for your design because we provide from two to nine outputs. Again, the 3.3V family does allow factory OTP customization if you have a particular setting that you would like to adjust, whether it's slew rate, output impedance, polarity of control signals, or even on the clock generators, maybe you prefer to run from a 20 MHz or 24 MHz reference clock instead of 25. That can easily be OTP into the parts.
We also have easy AC coupling to other logic standards such LVPECL, LVDS, and CML. There's SMBus programmability for the signal integrity and functionality. And again that can be OTP customized for your particular needs. And then we have 1.5 and 1.8V versions of the parts available for the more power-conscious applications that might be out there. As far as 3.3V size and power, this family ranges from a 4x4 mm at the smallest end to a 6x6 mm QFN in the largest part. These save up to 53% board area compared to IDT's legacy 3.3V current mode devices such as the 9DB803 for instance.
The integrated terminations allow you to save up to 36 resistors and that 36 resistors represent 62 mm2 of board area. So really great for space constrained designs. And then power-wise, the low power HCSL outputs allow up to an 80% power savings with the 3.3V parts. If you can use 1.5 or 1.8 in your design you can save even more power. The parts are easy to use because as shown earlier, the basic functions are controlled by hardware pins. So you do not need to use the SMBus for most applications. And we do have the individual OE pin on each PCIe output.
So the 3.3V full-featured PCIe clocks support Gen1, 2, 3, 4 common clock, SRIS and SRNS. It is a family of parts with a clock generator, fanout buffers, zero delay buffers, and clock multiplexers. And it supports both 100 ohm environments and 85 ohm environments without any external components. The numbering scheme is really easy. All parts start with a 9. And if you're looking for a generator it's a 9FG, the FG stands for frequency generator actually. If you're looking for a buffer, it's 9DB, for differential buffer. And if you're looking for a mux, it's 9DM, for differential mux. And then the operating voltage is the fourth character in the part number, L is for 3.3V, which stands for Low power. The V indicates 1.8V, or Very low power. And then the U indicates 1.5V, or Ultra-Low power.
The next two digits then provide the number of PCIe clock output pairs. So arranging from 1 all the way up to 9 currently. So that's the number of outputs. And then finally, the next to last digit indicates the output impedance. So a 33-ohm output impedance would have a 3 as the next to last digit. And then the device variant would be like 31, 32, 33, 34, etc. 100ohm output impedance has the next to last digit as a 4. And you would have 41, 42, 43, 44, etc. And then finally the 85-ohm output impedance starts with a 5 and that would be like 51, 52, 53, etc. That's it for the PCI Express family overview. Thank you for watching.
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
Watch the Video Series Below
- PCIe Clocking Architectures (Common and Separate)
- PCIe Separate Reference without Spread Clock Architecture
- PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Transcript
Hi, this is Ron Wade again with IDT. Today in this little episode we're gonna talk about PCI Express common clocking and its impact on the timing solutions that you would use in the system. So, as the name implies, common clocking says that all of the clocks come from one source. In this case it's a PLL. It may be spreading, it may not, but very seldom do you get all of your clocks from one device, so you'll need some sort of fan out buffers to distribute extra copies of the PCI Express clocks.
And while it's still a common clock, now we have to take into account whether we're using spread spectrum or whether we're using non-spread spectrum. If we are not using SFC, then we can fan out to these buffers here, and this could be a ZDB with a PLL inside, or it could be a fan out buffer, or it could be a part where you select between the two. Without spread spectrum, I can put this buffer in PLL mode or ZDB mode, it doesn't really matter and I don't violate the common clock requirement from the PCI Express sig. Same with this guy, it could be a fan out buffer or a PLL, ZDB, it doesn't really matter.
Things get really interesting though when spread spectrum is in use. When spread spectrum is in use then I have to have...this is my common clock. With spread spectrum in use, these have to be in fan out buffer mode. They cannot be used in PLL mode. And there's a couple of reasons for that, the simplest reason is that if this were a PLL, ZDB and it is tracking the spread, there will always be some tracking error, which means that as the input clock goes like this, the output clock is gonna overshoot it and go down like that. That's just the nature of having a PLL with finite bandwidth. So, you have tracking error here, and the tracking error will cause this to fall out of the PCI Express PPM limitations of +5,300 to -5,300 when you're using a half percent down-spread clock. So with SFC, you have your spread spectrum clock generator but any fan out buffer, any buffering at all has to be a fan out buffer without a PLL. That's a limitation on the architecture.
So the other point I'd like to make is as far as the jitter is concerned, because we're using a common clock here, to assume that the jitter on both sides for the clock is the same and all we have to do is take the difference function...that's a minus sign...the difference between the CPU and the CPU transmitter, say in the I/O storage receiver to calculate our jitter. That'll be more important when we get to the separate clocking in a future video.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
Watch the Video Series Below
- Edit Video page PCIe Clocking Architectures (Common and Separate)
- PCIe Common Clock Architecture and its Impact on Clocking
- PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
Watch the Video Series Below
- PCIe Clocking Architectures (Common and Separate)
- PCIe Common Clock Architecture and its Impact on Clocking
- PCIe Separate Reference without Spread Clock Architecture
Transcript
Hi, there. This is Ron Wade with IDT, and we're going to talk about separate reference independence spread today, which is the latest PCI express clocking architecture. So let's jump right in and define it and see what the implications are. So we have the CPU block here and we have our IO storage block here, and in this case they're both being clocked by a spreading clock source, two separate spreading clock sources, and we have the PCI link between them. So the whole idea of doing this is to keep from having to send the clock over this, let's say it's a cable, keep it from sending a clock over the cable like you have to do today.
So one of the implications of this, one is you don't have to send the clock over the cable when you have an SRIS system, but there's some other things to take into account, too. The first is the minimum PPM on this spreading clock is minus 5300 for the PCI, say. The maximum is plus 300 PPM. In this situation, this clock could be at minus 53. This could be at 300, but that means is that this link here has to...the controllers have to, number one, know they're in SRIS mode, and then insert what's called the skip ordered set or dummy data into the link. When you do that, you're going to lose from 1 to 3% of your performance. And the second issue here is there's no mechanism today for the ends of the link to know that they need to be in SRIS mode to insert those skip ordered sets. So there's no mechanism to say, "Hey, SRIS mode, please."
So the second item or the next item is that besides the difference in jitter performance between the transmitter and the receiver and the difference between the jitter of the clock over here and the clock over here, now we have two separate spreads to take into account, and I've drawn the frequency harmonics, the 32 kilohertz of harmonics here. So these have to be taken into account so there's a difference of the spreads also has to be noted. So it's much more stringent to have a clock that meets this requirement than the other architectures already discussed.
So the specifications, they're not final from the PCI-SIG on what a clock has to do to meet these requirements. Based on early indicators, we believe that we have clocks that are SRIS compatible today, and we can talk with you much more about that on one-on-one. So that's a high level overview of SRIS, a couple of system architectures you usually have to look out for, and if you have any questions, you can email me at [email protected]. Thanks.
An overview of IDT's full-featured PCI Express (PCIe) clock zero-delay buffers and fanout buffers addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, System Architect at IDT. For more information about IDT's PCIe zero-delay buffers and PCIe fanout buffers, visit http://www.idt.com/products/clocks-timing/application-specific-clocks/pci-express-clocks/pci-express-clock-buffers-and-multiplexers.
TRANSCRIPT
Hi there, this is Ron Wade with IDT. Welcome back to the third part of a five-part series on full-featured PCIe clocks. This part of the series covers zero-delay and fanout buffers. So focusing slightly on the 3.3-volt members of the family because those are the newest, we have zero delay buffers that range from two outputs up to eight outputs. These devices are gen 1 through 4 common clock compliant as well as gen 2 and 3 SRIS compliant. We offer parts with both 100-ohm and 85-ohm outputs so you can work in either industry standard or Intel server environments with no external termination components. Very important here also is the pin control of the PLL bandwidth, high or low, as well as PLL bypass mode.
The devices are offered in package sizes ranging from 4x4 to 6x6 millimeter QFN and with the DBL parts which are the 3.3-volt parts, we do have the ability to customize these parts via OTP at the factory for you. I'd like to emphasize that the standard parts are available off the shelf with no programming required, but we do have the ability to customize for you. For instance, you might want to have a different slew rate, you might want to change the default output amplitude, you may wish to have an output enabled pin with an active high polarity instead of an active low polarity. Well, we're able to do all of this at the factory very quickly and very easily.
The other thing I’d like to mention is that the 3.3-volt 9DBL parts are members of the full-featured PCIe zero-delay family which includes the 1.5 and 1.8-volt parts that have been in the market for a while. I’d like to just briefly review the key features here. We're meeting all of the upcoming phase jitter requirements for PCIe reference clocks today so that you can design your design today with these parts and then amortize that design over a couple of generations of devices.
The maximum power consumption of the DBL devices is a little bit over 211 milliwatts. That's the typical value at 3.3 volts which is a significant power savings over our legacy parts. This reduces heat dissipation and it also helps you meet EPA Energy Star requirements if that is something that your design is subject to. The integrated terminations are great because not only do they save you up to 32 resistors off of your BOM, they also save you up to 55 square millimeters of package area.
So the 9DBL parts are the newest member of our full-featured PCIe zero-delay buffer family which includes the 9DBV parts at 1.8 volts and the 9DBU parts at 1.5 volts. Again, the 3.3-volt parts are gen 1 through 4 and support the common clock, the SRnS and the SRIS clocking architectures. We're investigating these newer standards for the 1.5 and 1.8-volt parts, basically evaluating our characterization data to see how it stacks up and that process is ongoing. As far as pin compatibility goes, at the six and the eight output levels, you have pin compatibility across all three power supply voltages. And at the two and four output levels, the 1.5 and 1.8-volt parts share pin compatibility, the 3.3 volt part is slightly different.
So let's switch gears for a second to the fanout buffers. These are simpler than the ZDBs because they have no PLL inside. That means that they do have about 50 milliwatts or 40 milliwatts less power consumption and they support all of the upcoming PCI Express reference clock requirements for gen 4 and gen 2 and 3 SRIS. Again, the same 100-ohm and 85-ohm offerings in the family. These are pin compatible with the ZDBs. So, the 9DBL04 part is pin compatible with the 9DBL05, the 9DBL06 is pin compatible with the 9DBL07 and the 9DBL08 ZDB is pin compatible with a 9DBL09 fanout buffer.
These parts are available 5x5 to 6x6 millimeter QFN packages. OTP customization is available with the DBLs in the 3.3-volt family. And again, we have 1.5 and 1.8-volt versions of these devices available if, for instance, you need to emphasize additional power savings. So supporting all of the upcoming standards today means that you can again amortize your design over several generations of product, lowering your development costs. The 177 milliwatts cuts the power consumption greatly compared to legacy devices and also greatly aids in meeting EPA Energy Star requirements if that is something that your design is subject to. The integrated terminations with the fan-out buffers save up to 36 resistors eliminating them from your BOM as well as saving over 67 mm2 of board area.
So the full-featured PCIe fanout buffer family, again, we've got the 3.3-volt devices, the 9DBLs, the 9DBVs at 1.8, the 9DBUs at 1.5. And the DBLs being the newest, support the newest upcoming standards. We're evaluating the 1.5 and 1.8 to see what we can do with those to bring them into the newer generation performance requirements. Pin compatibility on the fanout buffers across all three operating voltage devices is seven and nine outputs and then pin compatibility at five outputs is limited to the 1.5 and 1.8-volt parts because the 3.3-volt part has a slightly different footprint.
Okay, so why would you use an eight-output 9DBL part instead of a 9DB108, 9DB833 device? Well, the main reason is performance. The performance standards are listed in the middle of the spec limit category here and then the actual performance of the various devices is listed under their column heading. So the DBL08 is on the right, it is the 3.3-volt ZDB. And it shows a little bit better improvement on the gen 1 peak-to-peak jitter but on gen two low-band and on gen three and four, it is significantly lower jitter than even the 9DB833 device which is the gen three part. The 9DB803 is only a gen two device. The 9DB108 mentioned at the top was only a gen one device and is not listed on this table. So the other thing that's in the 9DBL08 data sheet is 12k-20M additive phase jitter spec in fan-out buffer mode. And you won't find that on the older current mode legacy parts.
The big savings comes--besides the better performance--the big savings comes in reduced board area. You're going from over 100 mm2 down to 36 mm2. You're saving 32 resistors on your BOM and your typical power, even if you're using only 3.3 volts, is one-third of the legacy parts. If you care to power your outputs from 1.05 volts, you can actually reduce your power even further down to as low as 130 milliwatts. So why use the DBL08? Well, it's up to 70% less phase jitter, 64% less area, over 80% less power, 32 resistors taken off the BOM, and if you will need even more power savings, you can use the 1.8 volt or the 1.5-volt parts. Thank you for watching and stay tuned for the other parts in the series.
An overview of PCI Express applications and how IDT's industry-leading portfolio of PCIe clock products addresses the requirements. The video briefly discusses PCIe riser cards, embedded SOC, and PCIe storage (NVME) examples.
Presented by Ron Wade, System Architect at IDT.
Related Resources
Transcript
Hi there, this is Ron Wade. Welcome back to the last part of our series on full-featured PCIe clocks, part five of five, where we will discuss some of the applications for these parts. So, PCI Express applications are everywhere. The traditional places you might think to find them, such as data centers and servers and storage are still there. But PCI Express is growing into areas such as digital cameras, automotive infotainment systems, and consumer entertainment systems, as well.
We have a huge range of parts all the way from the smallest consumer application, to that largest networking and data center application. And the full-featured PCI Express family provides those enterprise levels of performance at the consumer size levels of space, power, and cost.
So one of the key applications for the full-featured PCIe family is PCI Express riser cards, where you are basically taking one clock from a connector and providing multiple clocks to additional connectors. Here I've shown the 9DBL02 device in a motherboard application where the riser card has two slots on it. So there would be a 9DBL02 fanout buffer either on the card itself, most likely, taking the clock from the system board and providing two copies, one to each of the connectors.
So, these parts again, common across all the full-featured devices. The performance levels against the PCI Express specifications give you reduced video error rates and then the zero delay buffers in this application help you manage PCI Express transport delay, although you can also use either this part in the fanout buffer mode or the pure fanout buffers as well. Again, the parts are offered in a 100ohm output impedance for that environment, and 85ohm output impedance which is often seen in the Intel application space.
Another key application for these is with embedded SoCs and here we're using an NXP QorIQ device that would be running in a single oscillator source clock mode, where the only clock into the SoC is a 100 MHz PCI Express clock, in this case coming from a 9FGL0841. These devices often have PCI Express SerDes on them, so I've shown this part driving two SerDes inside the NXP processor. And given that the A41 has eight output pairs, that leaves five additional outputs to drive other devices. I've also shown the pin out over here on the right. It's a 48-pin, 6x6 QFN and the footprint is shown at the bottom illustrating the 6x6 nature of the package.
The other growing application, key application, is PCI Express storage or sometimes called NVME. You've got PCI Express drives that are plugged into some sort of mezzanine or riser card. I've shown an IDT retimer in the brown box here, and you've got a system board which has PCI Express data going into the retimer, going up to the drives. Now the system board may be providing you with a clock, and if it is, then you would use a 9DBL device. A five output part is ideal because you've got one clock then going to the PCIe retimer and the other four clocks going to the four drives that are illustrated here.
If you're in an SRIS environment, the system board may not be providing you with a clock, in which case you would use a 9FGL device to generate the clocks. In this case, you would use the six-output part and have an extra one left over for other users, and it would drive the retimer and the four drives. That's it for the series, actually, of full-featured PCI Express parts. Thank you very much for watching and I hope you enjoyed it and learned something. Thanks.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT. For more information about IDT's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information, visit Renesas's PCIe Timing Solutions page.
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.