特長
- Low skew, low jitter PLL clock driver
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- With bypass mode mux
- Operating frequency 60 to 210 MHz
- Universal input (LVTTL, LVPECL, LVDS, LVCMOS)
説明
Not recommended for new designs
適用されたフィルター
読込中