特長
- 3 - HCSL CPU outputs
- 3 - HCSL Non-Spread SAS/SRC outputs
- 2 - HCSL SRC outputs
- 1 - HCSL DOT96 output
- 1 - 3.3V 48M output
- 3 - 3.3V PCI outputs
- 1 - 3.3V 14.318M output
- 0.5% down spread capable on CPU/SRC/PCI outputs
- Lower EMI
- 56-pin MLF package
- 21% space savings compared to 932SQ420 64-pin MLF
- Cycle to cycle jitter: CPU/SRC/NS_SRC/NS_SAS <50ps
- Phase jitter: PCIe Gen2 <3ps rms
- Phase jitter: PCIe Gen3
- Phase jitter: QPI 9.6GB/s <0.2ps rms
- Phase jitter: NS-SAS <0.4ps rms using raw phase data
- Phase jitter: NS-SAS <1.3ps rms using Clk Jit Tool 1.6.3
932SQ425 - Block Diagram
説明
The 932SQ425 is a reduced-pin-count main clock synthesizer for Intel Romley-generation server platforms. The 932SQ425 is driven with a 25 MHz crystal for maximum performance. It generates CPU outputs of 100 or 133.33 MHz.
