特長
- Four differential ECL/LVPECL level outputs
- One differential ECL/LVPECL or single-ended input (CLKA)
One differential HSTL or single-ended input (CLKB) - Maximum output frequency: 2.7GHz
- Additive phase jitter, RMS: 0.114ps (typical) at 156.25MHz
- Output skew: 50ps (maximum)
- LVPECL and HSTL mode operating voltage supply range:
VCC = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V - ECL mode operating voltage supply range:
VEE = -3.3V ± 5% or -2.5V ± 5%, VCC = 0V - -40 °C to 85 °C ambient operating temperature
- Lead-free (RoHS 6) packaging
8T33FS314I - Block Diagram
説明
The 8T33FS314I is a low skew 1-to-4 differential fanout buffer, designed with clock distribution in mind, accepting two clock sources into an input MUX. The MUX is controlled by a CLK_SEL pin. This makes the 8T33FS314I very versatile, in that, it can operate as both a differential clock buffer as well as a signal-level translator and fanout buffer.
The device is designed on a SiGe process and can operate at frequencies in excess of 2.7GHz. This ensures negligible jitter introduction to the timing budget which makes it an ideal choice for distributing high frequency, high precision clocks across backplanes and boards in communication systems. Internal temperature compensation guarantees consistent performance across various platforms.
