特長
- Two low skew, low additive jitter LVPECL output pairs
- Two selectable, differential clock input pairs
- Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
- Maximum input clock frequency: 2GHz
- Output skew: 5ps (typical)
- Propagation delay: 225ps (maximum)
- Low additive phase jitter, RMS, fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz: 36fs (maximum)
- Full 3.3V and 2.5V supply voltage
- Maximum device current consumption (IEE): 56mA (maximum)
- Available in lead-free (RoHS 6), 16-Lead VFQFN package
- -40°C to 85°C ambient operating temperature
8SLVP2102I - Block Diagram
説明
The 8SLVP2102I is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP2102I is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP2102I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers, RF Buffers |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |
