特長
- Four low-skew, low additive jitter LVPECL differential output pairs
- Differential LVPECL input pair can accept the following differential input levels: LVDS, LVPECL, CML
- Differential PCLKx pairs can also accept single-ended LVCMOS levels
- Maximum input clock frequency: 2GHz
- LVCMOS interface levels for the control input (input select)
- Output skew: 5ps (typical)
- Propagation delay: 320ps (maximum)
- Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz to 20MHz: 40fs (maximum)
- Maximum device current consumption (IEE): 60mA (maximum)
- Full 3.3V or 2.5V supply voltage
- Lead-free (RoHS 6) packaging
- -40 °C to 85 °C ambient operating temperature
8SLVP1104I - Block Diagram
説明
The 8SLVP1104I is a high-performance differential LVPECL fanout buffer designed for the fanout of high-frequency, very-low additive phase noise clock and data signals. The 8SLVP1104I is characterized for operation from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1104I ideal for clock distribution applications demanding well-defined performance and repeatability. Four low-skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low-power consumption and low-additive phase noise.
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers, RF Buffers |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 3.0 x 3.0 x 1.0 | 16 | 0.5 |
