パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG72 |
| Lead Count (#): | 72 |
| Pkg. Dimensions (mm): | 10.0 x 10.0 x 1.0 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 72 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Country of Assembly | TAIWAN |
| Country of Wafer Fabrication | SINGAPORE |
| Channels (#) | 8 |
| Core Voltage (V) | 2.5V, 3.3V |
| Diff. Inputs | 2 |
| Diff. Outputs | 12 |
| Family Name | ClockMatrix |
| Fractional Output Dividers (#) | 8 |
| Function | Multi-channel DPLL / DCO |
| Input Freq (MHz) | 0.001 - 1000 |
| Input Type | HCSL, LVDS, LVHSTL, LVPECL, SSTL |
| Inputs (#) | 4 |
| Length (mm) | 10 |
| MOQ | 2500 |
| Output Banks (#) | 8 |
| Output Freq Range (MHz) | 5.0E-7 - 1000 |
| Output Skew (ps) | 50 |
| Output Type | HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL |
| Output Voltage (V) | 1.2V, 1.5V, 1.8V, 2.5V, 3.3V |
| Outputs (#) | 24 |
| Phase Jitter Max RMS (ps) | 0.2 |
| Phase Jitter Typ RMS (ps) | 0.15 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 1.0 |
| Pkg. Type | VFQFPN |
| Product Category | Clock Matrix |
| Prog. Interface | I2C, SPI |
| Reel Size (in) | 13 |
| Reference Output | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 10 |
| Xtal Freq (KHz) | 25 - 54 |
| 掲載 | No |
8A34045 に関するリソース
説明
The 8A34045 multi-channel Digital PLL/Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion, and timing paths for common communications protocols such as Synchronous Ethernet (SyncE), Optical Transport Network (OTN), and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. DCOs are available to be controlled by OTN clock recovery servo software running on an external processor. DPLLs support the filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for clock generation, jitter attenuation, and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.