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OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE

パッケージ情報

CADモデル:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG20
Lead Count (#):20
Pkg. Dimensions (mm):6.5 x 4.4 x 1.0
Pitch (mm):0.65

環境及び輸出分類情報

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

製品スペック

Lead Count (#)20
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)74
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
App Jitter ComplianceSTM-1 (OC-3/STS-3), STM-4 (OC-12/STS-12)
Core Voltage (V)3.3
Divider Value1, 4
Feedback Divider1 - 1
Feedback InputNo
Input Freq (MHz)19.44 - 19.44
Input TypeLVCMOS, LVDS, LVPECL
Inputs (#)2
Length (mm)6.5
MOQ3034
Output Banks (#)1
Output Freq Range (MHz)155.52 - 155.52, 622.08 - 622.08
Output SignalingLVPECL
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)2
Package Area (mm²)28.6
Pitch (mm)0.65
Pkg. Dimensions (mm)6.5 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryGeneral Purpose Clocks
Prog. ClockNo
Reference OutputNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumNo
Tape & ReelNo
Thickness (mm)1
VCO Max Freq (MHz)621
VCO Min Freq (MHz)622
Width (mm)4.4

説明

The 894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retimed data signals.