パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | SOIC |
| Pkg. Code: | PSG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 12.8 x 7.6 x 2.34 |
| Pitch (mm): | 1.27 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 20 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 37 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Advanced Features | Feedback Input |
| C-C Jitter Max P-P (ps) | 35 |
| Core Voltage (V) | 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 62.5 - 1000 |
| Input Type | HSTL, LVDS, LVPECL, SSTL |
| Inputs (#) | 1 |
| Length (mm) | 12.8 |
| MOQ | 37 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 62.5 - 1000 |
| Output Type | LVDS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 1 |
| Package Area (mm²) | 97.3 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 12.8 x 7.6 x 2.34 |
| Pkg. Type | SOIC |
| Product Category | Zero Delay Buffers |
| Prog. Clock | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 2.34 |
| Width (mm) | 7.6 |
874S02I に関するリソース
説明
The 874S02I is a highly versatile 1:1 Differential-to-LVDS Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 874S02I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz to 1GHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.