特長
- One differential input reference clock
- Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
- Integrated input termination resistors
- Eight LVDS outputs
- Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
- Maximum input clock frequency: 500MHz
- LVCMOS interface levels for the control inputs
- Internal regulator for improved noise immunity
- Individual output enable/disabled by I2C interface
- Output skew: 28ps
- Additive Phase Jitter, RMS: 0.168ps (typical), 125MHz
- Low additive phase jitter
- Full 2.5V supply voltage
- Available in Lead-free (RoHS 6) package
- -40°C to 85°C ambient operating temperature
874208I - Block Diagram
説明
The 874208I is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 874208I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 874208I ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up, all outputs are enabled.
