特長
- Eight LVCMOS/LVTTL outputs, (2 banks of 4 outputs) Each output has individual synchronous output enable
- Two selectable differential CLKx, nCLKx inputs
- Dual differential input pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Maximum output frequency: 250MHz
- Selectable ÷1 or ÷2 operation
- Glitchless output behavior during input switch
- Output skew: 50ps (typical), 3.3V
- Bank skew: 30ps (typical), 3.3V
- Supply modes: Core/Output 3.3V/3.3V 2.5V/2.5V 3.3V/2.5V
- 0°C to 70°C ambient operating temperature
- Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
説明
The 870S208 is a low skew, 8 output LVCMOS / LVTTL Fanout Buffer with selectable divider. The 870S208 has 2 selectable inputs that accept a variety of differential input types. The device provides the capability to suppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. The low impedance LVCMOS outputs are designed to drive 50? series or parallel terminated transmission lines. The effective fanout can be increased from 8 to 16 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The output enable pins assigned to each output, support enabling and disabling of each output individually. The 870S208 is characterized at full 3.3V and 2.5V, and mixed 3.3V/2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 870S208 ideal for high performance, single ended applications.
