概要
説明
The 8624I is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer. The 8624I has two selectable clock input pairs. The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 630MHz. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 630MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications..
特長
- Fully integrated PLL
- Five differential HSTL compatible outputs
- Selectable differential CLKx, nCLKx input pairs
- CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
- Output frequency range: 31.25MHz to 630MHz
- Input frequency range: 31.25MHz to 630MHz
- VCO range: 250MHz to 630MHz
- External feedback for "zero delay" clock regeneration
- Cycle-to-cycle jitter: 35ps (maximum)
- Output skew: 50ps (maximum)
- Static phase offset: 30ps ±125ps
- 3.3V core, 1.8V output operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free RoHS-compliant packages
- For replacement device use 8725BY-01LF
